Apparatuses and methods for concentrated arrangement of amplifiers. An example apparatus may include a first amplifier circuit including a first and second transistors. The first width different from the second width, the first length different from the second length. The apparatus further including a second amplifier circuit including a third and fourth transistors. The first transistor including a first gate electrode and the third transistor having a third gate electrode each having a first length and a first diffusion region and a third diffusion region, respectively, each having a first width, and the second transistor including a second gate electrode and the fourth transistor having a fourth gate electrode each with a fourth length and a second diffusion region and a fourth diffusion region, respectively, each having a second width. The first and third transistors are collectively arranged and the second and fourth transistors are collectively arranged.

An electronic device may include a sensing circuit and a current subtraction circuit. The sensing circuit may output first and second current signals. The current subtraction circuit may mirror the first and second current signals onto first and second current branches. The second current branch may be split into a first sub-path and a second sub-path. An amplifier may control the amount of current flowing through the second sub-path by forcing the current flowing through the first current branch and the current flowing through the first sub-path to be identical. Configured in this way, the current flowing through the second sub-path will be equal to the difference between the first and second current signals. The current flowing through the second sub-path may be optionally amplified using another current mirror.

A reference voltage generator includes a voltage generation circuit, an amplifier, a diode unit and a transistor. The voltage generation circuit includes an output terminal for outputting a reference voltage, a first terminal having an operational voltage, and a second terminal. The amplifier includes an input terminal coupled to the first terminal of the voltage generation circuit, an output terminal, a first terminal coupled to a first voltage terminal, and a second terminal. The diode unit includes a first terminal coupled to the second terminal of the amplifier, and a second terminal coupled to the second terminal of the voltage generation circuit and a second voltage terminal. The transistor includes a first terminal coupled to the first terminal of the amplifier, a second terminal coupled to the output terminal of the voltage generation circuit, and a control terminal coupled to the output terminal of the amplifier.

Examples of circuits and amplifiers include recirculation circuitry to reduce or cancel error currents produced by target bipolar junction transistors (BJTs). In an example, first recirculation circuitry is coupled to the base of a first signal-conveyance BJT and to one of the collector or the emitter of the first signal-conveyance BJT; second recirculation circuitry is coupled to the base of a second signal-conveyance BJT and to one of the collector or the emitter of the second signal-conveyance BJT; and biasing circuitry is coupled to the first and second recirculation circuitry. The recirculation circuitry may be implemented with BJTs or MOSFETs. Configurations are provided in which error current(s) are recirculated between the base and collector/emitter node of each target BJT.

Apparatuses and methods for concentrated arrangement of amplifiers. An example apparatus may include a first amplifier circuit including a first and second transistors. The first width different from the second width, the first length different from the second length. The apparatus further including a second amplifier circuit including a third and fourth transistors. The first transistor including a first gate electrode and the third transistor having a third gate electrode each having a first length and a first, diffusion region and a third diffusion region, respectively, each having a first width, and the second transistor including a second gate electrode and the fourth transistor having a fourth gate electrode each with a fourth length and a second diffusion region and a fourth diffusion region, respectively, each having a second width. The first and third transistors are collectively arranged and the second and fourth transistors are collectively arranged.

A reference voltage generator includes a voltage generation circuit, an amplifier, a diode unit and a transistor. The voltage generation circuit includes an output terminal for outputting a reference voltage, a first terminal having an operational voltage, and a second terminal. The amplifier includes an input terminal coupled to the first terminal of the voltage generation circuit, an output terminal, a first terminal coupled to a first voltage terminal, and a second terminal. The diode unit includes a first terminal coupled to the second terminal of the amplifier, and a second terminal coupled to the second terminal of the voltage generation circuit and a second voltage terminal. The transistor includes a first terminal coupled to the first terminal of the amplifier, a second terminal coupled to the output terminal of the voltage generation circuit, and a control terminal coupled to the output terminal of the amplifier.

Apparatuses and methods for concentrated arrangement of amplifiers. An example apparatus may include a first amplifier circuit including a first and second transistors. The first width different from the second width, the first length different from the second length. The apparatus further including a second amplifier circuit including a third and fourth transistors. The first transistor including a first gate electrode and the third transistor having a third gate electrode each having a first length and a first, diffusion region and a third diffusion region, respectively, each having a first width, and the second transistor including a second gate electrode and the fourth transistor having a fourth gate electrode each with a fourth length and a second diffusion region and a fourth diffusion region, respectively, each having a second width. The first and third transistors are collectively arranged and the second and fourth transistors are collectively arranged.

A receiver circuit includes: a constant current circuit to generate second paired current signals according to first paired current signals; a current splitter circuit to output third paired current signals generated from the second paired current signals, from a first output node and a second output node; and a differential TIA circuit to output paired voltage signals from a first output terminal and a second output terminal, according to the third paired current signals input from a third input node and a fourth input node. The differential TIA circuit includes a first feedback resistor element connected between the third input node and the second output terminal, and a second feedback resistor element connected between the fourth input node and the first output terminal. Average voltages of the first and second output nodes and the first and second output terminals are set to be equivalent to each other.

Systems and methods for providing a high performance current source are described. In an example implementation, the current source includes transistors in dual current mirror configuration. The dual mirror configuration employs current feedback to increase the output resistance of the current source while achieving a wide voltage swing.

System and method for error amplification and processing. For example, the system includes: a signal processing unit configured to receive a reference signal and a feedback signal and generate a digital pulse signal, a frequency of the digital pulse signal being associated with a difference between the reference signal and the feedback signal; a counter configured to receive the digital pulse signal and generate a counter output signal based on at least information associated with the digital pulse signal; and a digital-to-analog converter configured to receive the counter output signal and generate an output signal based on at least information associated with the counter output signal.