An operational amplifier integrated circuit includes a differential pair of transistors having a first input, a second input. A bias current generator applies a bias current to an output of the differential pair of transistors. A control loop generates a control voltage arising from a difference in potentials between the first input and the second input. An additional current that is added to the bias current is generated in response to the control voltage.

Disclosed examples include differential amplifier circuits and variable neutralization circuits for providing an adjustable neutralization impedance between an amplifier input node and an amplifier output node, including neutralization impedance T circuits with first and second impedance elements in series between the amplifier input and output, and a third impedance element, including a first terminal connected to a node between the first and second impedance elements, and a second terminal connected to a transistor. The transistor operates according to a control signal to control the neutralization impedance between the amplifier input node and the amplifier output node.

Provided is an interpolation operational amplifier circuit, including: at least two sets of differential input pair transistors, each differential input pair transistor including first and second transistors, wherein base terminals of the first and second transistors are electrically connected to serve as a base terminal of the differential input pair transistor, and source electrodes of the first and second transistors are electrically connected to serve as a source electrode of the differential input pair transistor; and a voltage control unit electrically connected to the base terminal and source electrode of the differential input pair transistor, and configured to control a voltage of the base terminal of the P-type differential input pair transistor to be smaller than the first power supply voltage, and/or to control a voltage of the base terminal of the N-type differential input pair transistor to be larger than the second power supply voltage.

An operational amplifier includes a first amplifying unit, a second amplifying unit, a current source, a first compensation capacitor, and a second compensation capacitor. The first amplifying unit includes a first input transistor, a second input transistor, a third input transistor, and a fourth input transistor. The second amplifying unit includes a fifth input transistor, a sixth input transistor, a seventh input transistor, and an eighth input transistor. One end of the first compensation capacitor is coupled to a drain of the seventh input transistor, and the other end of the first compensation capacitor is coupled to a gate of the eighth input transistor. One end of the second compensation capacitor is coupled to a drain of the eighth input transistor, and the other end of the second compensation capacitor is coupled to a gate of the seventh input transistor.

The present disclosure relates to a differential input circuit, an amplifier circuit, and a display device. The differential input circuit comprises: a first power module, a second power module, a first shunt module, a second shunt module, a first output module, and a second output module. The first power module is controlled to output a first signal, a second signal, and a third signal through a first bias signal, and the second power module receives the first signal, and outputs a fourth signal and a fifth signal through a differential input signal. The first shunt module, the second shunt module, the first output module, and the second output module are controlled by the differential input signal so that the first output module and the second output module output signals under the control of the differential input signal.

The present disclosure provides a power amplifier and an electrical device. The two-stage power amplifier architecture is tuned staggered before power combining. A previous stage matching network and its input matching are split into a cascaded staggered tuning, such that the center frequency is at frequency point 1 less than the design frequency point and frequency point 2 greater than design frequency point, and then the power combining stage is tuned at the design frequency point. At advanced process nodes (such as 65 nm or below), compared with the known architecture, in-band signal quality and out-of-band filtering effect of the power amplifier chip integrating this architecture will be better when using the same number of transformers (same area), the reliability will be better. Due to its good flatness within the band, this architecture is especially suitable for carrier aggregation communication occasions.

An amplifier includes an amplification circuit, an equalization circuit, an output circuit, a first gain adjusting circuit, and a second gain adjusting circuit. The amplification circuit changes voltage levels of first and second amplification nodes based on first and second input signals. The equalization circuit changes the voltage levels of the first and second amplification nodes. The output circuit generates an output signal based on the voltage levels of the first and second amplification nodes. The first gain adjusting circuit changes voltage levels applied to the first and second amplification nodes based on the voltage levels of the first and second amplification nodes and a first gain control signal. The second gain adjusting circuit changes a voltage level of the output signal based on a second gain control signal.

Disclosed examples include differential amplifier circuits and variable neutralization circuits for providing an adjustable neutralization impedance between an amplifier input node and an amplifier output node, including neutralization impedance T circuits with first and second impedance elements in series between the amplifier input and output, and a third impedance element, including a first terminal connected to a node between the first and second impedance elements, and a second terminal connected to a transistor. The transistor operates according to a control signal to control the neutralization impedance between the amplifier input node and the amplifier output node.

According to an aspect, a low dropout (LDO) voltage regulator includes a differential amplifier, a pass transistor coupled to an output of the differential amplifier, where the pass transistor is configured to provide an output voltage of the LDO voltage regulator, and a soft-start circuit coupled to the differential amplifier. The soft-start circuit is configured to adjust a soft-start driving signal to control a slope of the output voltage based on the output voltage during a start-up operation of the LDO voltage regulator.

Embodiments of the disclosure are drawn to apparatuses and methods for testing the resistance of through silicon vias (TSVs) which may be used, for example, to couple multiple memory dies of a semiconductor memory device. A force amplifier may selectively provide a known current along a mesh wiring structure and through the TSV to be tested. The force amplifier may be positioned on a vacant area of the memory device, while the mesh wiring structure may be positioned in an area beneath the TSVs of the layers of the device. A chopper instrumentation amplifier may be selectively coupled to the TSV to be tested to amplify a voltage across the TSV generated by the current passing through the TSV. The chopper instrumentation amplifier may be capable of determining small resistance values of the TSV.