A low energy transmitter is provided. The transmitter includes an antenna circuit wherein the antenna circuit has an antenna positive node interface (Vop) and an antenna negative node interface (Von); a reference voltage source that supplies a reference voltage to the antenna circuit; and a common mode feedback (CMFB) circuit coupled to the antenna circuit that receives from the antenna circuit inputs from the Vop and the Von and supplies at least one signal to the antenna circuit.

An amplifier includes an input circuit that amplifies a difference between a first input voltage and a second input voltage to generate a first current and a second current. A positive feedback circuit amplifies a difference between the first current and the second current to generate a third current and a fourth current and outputs a difference between the third current and the fourth current through an output node. A temperature compensation circuit adjusts an amplification factor of the positive feedback circuit in response to a change of temperature.

An image sensor may include an array of image sensor pixels. The array of image sensor pixels may be controlled by row driver circuitry. The row driver circuitry may include row drivers that receive power supply signals from transconductance amplifier circuitry. The transconductance amplifier circuitry may include multiple amplifiers with output ports shorted to one another. Each amplifier may include input transistors, cross-coupled transistors with a low threshold voltage, and additional transistors coupled in series with the cross-coupled transistors and having a moderate or high threshold voltage.

An example VGA includes a transistor arrangement having a plurality of transistors configured to realize one or more gain step circuits of the VGA, and a cross-couple switching arrangement having a plurality of switches configured to selectively change the coupling of the terminals of at least some of the transistors depending on whether a given gain step circuit is supposed to be in an ON state or in an OFF state. Using the cross-couple switching arrangement advantageously allows keeping all of the transistors ON at all times during operation and changing the coupling of some transistor terminals to either realize an in-phase addition of currents flowing through various transistors to apply the maximum gain or realize a subtraction of currents to apply the minimum gain. Such a VGA may be inherently wideband, enabling a highly linear, wideband operation without having to resort to significant trade-offs with other performance parameters.

Multi-stage auto-zeroing signal amplifiers are deployed within event-shuttering pixels of a quanta image sensor (QIS) pixel array to enable reliable per-pixel reporting of photonic events, down to resolution of a single photon strike, for each of a continuous sequence of sub-microsecond event-detection intervals.

According to one embodiment, there is provided a semiconductor device comprising a first differential amplifier circuit. The first differential amplifier circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor. The second transistor's gate and drain are connected to the first transistor. The third transistor is diode-connected through the first transistor or diode-connected without passing through the first transistor. Thea fourth transistor is diode-connected through the second transistor or diode-connected without passing through the second transistor. The fifth transistor forms a first current mirror circuit with the third transistor. The sixth transistor is connected to a drain of the first transistor in parallel with the third transistor and forms a second current mirror circuit with the fifth transistor.

In one example an amplifier includes a bias circuit, an open-loop gain stage including a first PMOS having a gate coupled to a first node, a source coupled to a second node, a drain coupled to a third node, and a bulk coupled to the bias circuit, a second PMOS having a gate coupled to a ground node, a source coupled to the second node, a drain coupled to a fourth node, and a bulk coupled to the bias circuit, a first NMOS having a drain and a gate coupled to the third node and a source coupled to a fifth node, a second NMOS having a drain coupled to the fourth node, a gate coupled to the third node, and a source coupled to the fifth node, an adjustable resistor coupleable between the third and fourth nodes, and a buffer stage coupled to the open-loop gain stage.

A differential transimpedance amplifier includes a first pair of common-gate amplifiers having a first NMOS transistor and a second NMOS transistor configured in a cross-coupling topology using a first capacitor and a second capacitor, a second pair of common-gate amplifiers comprising a first PMOS transistor and a second PMOS transistor configured in a cross-coupling topology using a third capacitor and a fourth capacitor, wherein an output of the first pair of common-gate amplifiers and an output of the second pair of common-gate amplifiers are coupled via a fifth capacitor and a sixth capacitor.

An operational amplifier integrated circuit includes a differential pair of transistors having a first input, a second input. A bias current generator applies a bias current to an output of the differential pair of transistors. A control loop generates a control voltage arising from a difference in potentials between the first input and the second input. An additional current that is added to the bias current is generated in response to the control voltage.

In one example an amplifier includes a bias circuit, an open-loop gain stage including a first PMOS having a gate coupled to a first node, a source coupled to a second node, a drain coupled to a third node, and a bulk coupled to the bias circuit, a second PMOS having a gate coupled to a ground node, a source coupled to the second node, a drain coupled to a fourth node, and a bulk coupled to the bias circuit, a first NMOS having a drain and a gate coupled to the third node and a source coupled to a fifth node, a second NMOS having a drain coupled to the fourth node, a gate coupled to the third node, and a source coupled to the fifth node, an adjustable resistor coupleable between the third and fourth nodes, and a buffer stage coupled to the open-loop gain stage.