A wideband power amplifier (PA) linearization technique is proposed. A current interpolation technique is proposed to linearize power amplifiers over a wide bandwidth. The wideband power amplifier linearization technique employs a novel transconductance Gm linearizer using a current interpolation technique that achieves improvement in the third order intermodulation over wide bandwidth for a sub-micron CMOS differential power amplifier. By using a small amount of compensating bias into an opposite phase differential pair, linearization over wide bandwidth is achieved and can be optimized by adjusting the compensating bias.

A circuit and method for starting-up a crystal oscillator is described. A crystal resonator is configured to be coupled to a start-up circuit including an H-bridge circuit having a number of switches. A plurality of switch control signals are generated in response to detecting a zero-crossing event of the motional current in the crystal resonator. The switches of the H-bridge circuit are controlled by the switch control signals to apply a voltage to the terminals of the crystal resonator in a first polarity during a first switch control phase and a second opposite polarity during a second switch control phase. During a respective first subphase of the respective switch control phase, the plurality of switches are configured in a first configuration to couple the supply node to a respective crystal resonator terminal. During a respective second subphase of the respective switch control phase the plurality of switches are configured in a second configuration to couple the supply node to the respective crystal resonator terminal. The resistance between the supply node and the respective crystal resonator terminal is larger in the second configuration than the first configuration. A zero-crossing is detected during each respective second sub-phase.

A first embodiment is directed to a circuit including a positive biasing circuit with a drive PMOS for biasing in subthreshold, a negative biasing circuit with a drive NMOS for biasing in subthreshold, and an amplification circuit coupled to the biasing circuits. The amplification circuit includes a first stage with a first boosting stage, a second stage with a second boosting stage, and a resistive element coupled between the first and second stages. A second embodiment is directed to a folded cascode operational amplifier wherein a value of the resistive element is selected to place at least one of a drive MOS in subthreshold. A third embodiment is directed to an integrated circuit with a resistive area neighboring a first boosting area and a second boosting area, the resistive area including a resistive element directly connected to a drive PMOS and a drive NMOS.

An amplifier circuit includes a differential input terminal, a first power supplier, an amplifier, and a current redistributor. A differential input terminal includes a first differential pair of a p-type and a second differential pair of an n-type, and receives an input voltage. A first power supplier supplies a bias current to the differential input terminal. An amplifier receives an output current of the first differential pair and an output current of the second differential pair, and applies an amplified current to an output node. A current redistributor receives the output current of the first differential pair and the output current of the second differential pair, and provides a redistribution current to the differential input terminal.

An operational amplifier includes a first transistor, a second transistor, a third transistor, a first constant current source, an output state, a first switch, and a second switch. The first transistor has a first gate configured to receive an output voltage from an output node. The second transistor has a second gate. The third transistor has a third gate configured to receive an input voltage. The first constant current source is coupled to sources of the first transistor, the second transistor, and the third transistor. The output stage is configured to drive the output voltage on the output node based on a first current through the first transistor, a second current through the second transistor, and a third current through the third transistor. The first switch is coupled between the second gate of the second transistor and the third gate of the third transistor; and the second switch is coupled between the output node and the second gate of the second transistor.

Provided is an input voltage endurance protection architecture applied to a high-voltage operational amplifier with high input amplitude and high linearity. The input voltage endurance protection architecture includes three parts: a main operational amplifier, an auxiliary operational amplifier and an input stage voltage endurance protection circuit. The main operational amplifier is a high-voltage general-purpose operational amplifier, the auxiliary operational amplifier is a single-stage differential amplifier, and the single-stage differential operational amplifier is connected to a degeneration resistor Rbias. In addition, the auxiliary operational amplifier has a same connection method as the main operational amplifier at a positive input terminal and a negative input terminal, and both the positive input terminal and the negative input terminal are protected by an input stage voltage endurance protection circuit and receive and process input signals simultaneously.

An input receiver includes a first current source circuit, a second current source circuit, a first rail-to-rail amplifier circuit, a first inverter circuit, and a second inverter circuit. The first current source circuit adjusts an operating current flowing through a first node according to a first bias signal. The second current source circuit adjusts a ground current flowing through a second node according to a second bias signal. The first rail-to-rail amplifier circuit and the first inverter circuit are connected in parallel between the first node and the second node. The first rail-to-rail amplifier circuit receives an input signal and compares the input signal with a reference voltage and accordingly outputs an amplified signal. The second inverter circuit is coupled between an operating voltage and a ground voltage. The second inverter circuit generates an output signal according to an inverted signal outputted by the first inverter circuit.

Storage devices are capable of utilizing receiver devices with native devices configured to support lower voltage supplies for higher read performances. The receiver device may include a current source circuit, first and second stage circuits, and a duty cycle balancer circuit. The first stage circuit may utilize first and second native devices with a threshold voltage (VTH) that enables proper lower voltage operations in saturation at high speeds. The current source stage circuit may utilize a third native device to track a transconductance and provide a reference current that becomes proportional to VTH to maintain tighter gain across process, variation, and temperature (PVT). The second stage circuit may utilize a current folding stage to provide a high gain for faster conversion of intermediate signals. The duty cycle balancer may utilize a fourth native device to balance a rise and fall delay skew across the PVT to maintain tighter duty cycle.

Numerous embodiments for processing the current output of a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. The embodiments comprise a summer circuit and an activation function circuit. The summer circuit and/or the activation function circuit comprise circuit elements that can be adjusted in response to the total possible current received from the VMM to optimize power consumption.

A circuit and method for starting-up a crystal oscillator is described. A crystal resonator is configured to be coupled to a start-up circuit including an H-bridge circuit having a number of switches. A plurality of switch control signals are generated in response to detecting a zero-crossing event of the motional current in the crystal resonator. The switches of the H-bridge circuit are controlled by the switch control signals to apply a voltage to the terminals of the crystal resonator in a first polarity during a first switch control phase and a second opposite polarity during a second switch control phase. During a respective first subphase of the respective switch control phase, the plurality of switches are configured in a first configuration to couple the supply node to a respective crystal resonator terminal. During a respective second subphase of the respective switch control phase the plurality of switches are configured in a second configuration to couple the supply node to the respective crystal resonator terminal. The resistance between the supply node and the respective crystal resonator terminal is larger in the second configuration than the first configuration. A zero-crossing is detected during each respective second sub-phase.