A CMOS channel select filter for DVB-H direct-conversion receives based on a transresistance amplifier (TRA) is disclosed. The channel select filter includes a fully differential transresistance amplifier (FDTRA) configured to change an input current at each differential input terminal to a voltage at each differential output terminal based on an impedance at a corresponding differential impedance terminal. The channel select filter also includes two feedback resistors, each having one end connected to a respective differential output terminal of the FDTRA and having another end connected to the node, two first capacitors, each connected between ground and the node, and two second capacitors, each connected between ground and a respective differential impedance terminal.

Various technologies pertaining to a high-impedance current source are described herein. The current source outputs a substantially constant current by way of a first transistor that draws current from a supply. The current source is configured to feed back noise from the supply to a feedback resistor at an input of an operational amplifier (op-amp) by way of a second transistor. The feedback resistor and the op-amp are configured such that responsive to receiving the supply noise feedback, the op-amp drives a gate voltage of the first transistor to cause the first transistor to reject the supply noise and cause the output of the current source to remain substantially constant.

Examples relate to a buffered flipped voltage follower circuit arrangement, low dropout voltage regulators, a capacitive digital-to-analog converter, a transceiver for wireless communication, a mobile communication device, a base station transceiver, and to a method for forming a buffered flipped voltage follower circuit arrangement. The buffered flipped voltage follower circuit arrangement comprises a first transistor (M.sub.p) comprising a first terminal, a second terminal and a gate terminal. The buffered flipped voltage follower circuit arrangement comprises a second transistor (M.sub.c) comprising a first terminal, a second terminal and a gate terminal. The buffered flipped voltage follower circuit arrangement comprises a buffer circuit comprising an input terminal and an output terminal. The buffered flipped voltage follower circuit arrangement a feed-forward compensation circuit (?g.sub.mf) comprising an input terminal and an output terminal. The first terminal of the first transistor (M.sub.p) is coupled to a supply voltage of the flipped voltage follower circuit. The second terminal of the first transistor (M.sub.p) is coupled with the first terminal of the second transistor (M.sub.c) and with an output voltage terminal of the buffered flipped voltage follower circuit arrangement. The second terminal of the second transistor (Mc) is coupled with the input terminal of the buffer circuit and with the output terminal of the feed-forward compensation circuit (?g.sub.mf). The gate terminal of the first transistor (MP) is coupled with the output terminal of the buffer circuit and with the input terminal of the feed-forward compensation circuit (?g.sub.mf).

In a differential amplifier circuit, a differential amplifier circuit unit includes: first and second transistors provided between a current source circuit and a load circuit, which receives differential input signals at gates to generate differential output signals at drains; and a third transistor connected between sources of the first and second transistors, which receives a control signal at a gate. A replica amplifier circuit unit includes: a voltage generation circuit which generates first and second reference voltages; first and second replica transistors which receives the first and second reference voltages at gates to generate replica output signals at drains; a third replica transistor connected between sources of the first and second replica transistors, which receives the control signal at a gate; and an operational amplifier which generates the control signal according to a difference between at least one of the first and second reference voltages and the replica output signal.

In some examples, an amplifier includes a pair of input differential transistors a pair of feedback transistors, a pair of current sources, a pair of gain setting resistors, and a tail current transistor. Control terminals of the feedback transistors are respectively coupled to first terminals of the input differential transistors. The pair of current sources are respectively coupled to the control terminals of the feedback transistors and the first terminals of the input differential transistors. The pair of gain setting resistors have first terminals that are respectively coupled to the second terminals of the input differential transistors. The pair of gain setting resistors have second terminals that are coupled to one another. The tail current transistor has a first terminal coupled to the second terminals of the gain setting resistors and a second terminal coupled to a DC supply.

Circuits and methods for switched mode operational amplifiers are provided. In some embodiments, circuits are provided, the circuits comprising: an amplifier having an output; a first pulse width modulator (PWM) having an input coupled to the output of the amplifier and using a first periodic reference signal waveform; and a second PWM having an input coupled to the output of the amplifier and using a second periodic reference signal waveform, wherein the second periodic reference signal waveform is 180 degrees out of phase from the first periodic reference signal waveform. In some embodiments, circuits are provided, the circuits comprising: an amplifier having an output; and a plurality of pulse width modulators (PWMs) each having an input coupled to the output of the amplifier and using a corresponding unique one of a plurality of periodic reference signal waveforms, wherein the plurality of periodic reference signal waveforms are shifted in phase.

This applications relates to methods and apparatus for amplifying signals from capacitive transducers, in particular MEMS transducers such as MEMS capacitive microphones. An amplifier circuit has a transducer biasing node (102) for outputting a transducer bias voltage for biasing the capacitive transducer (101) and a signal node (103) for receiving the input signal (V.sub.in). An amplifier arrangement (108) comprising a feedback resistor network (304, 305) provides an amplified output signal (V.sub.out). A voltage buffer (306) provides a buffered bias voltage at a buffer node (307) which is connected to a terminal of the feedback resistor network, to at least partly define the quiescent level of the output signal. The buffer node (307) is electrically coupled to the transducer biasing node (102) via a capacitance (106) which may form part of a bias filter.

A two-stage operational amplifier is provided to comprise a bias voltage generator, a first stage operational amplifier and a second stage operational amplifier, wherein the first stage operational amplifier comprises a folded cascode amplifier circuit and a cross coupling load, the cross coupling load is coupled to a load differential pair in the folded cascode amplifier circuit, the cross coupling load comprises two transistors, the two transistors in the cross coupling load and two transistors in the load differential pair constitute two current mirror structures, which are cross coupled. In the solution, the cross coupling load is added to the load differential pair in the folded cascode amplifier circuit, to increase gain of the two-stage operational amplifier by using positive feedback and negative conductance gain enhancement technology; while parameters of MOSFETs in the folded cascode amplifier circuit are properly set to reduce noise of the two-stage operational amplifier.

An amplifier may include a main signal path having a plurality of stages compensated by feedback elements, the plurality of stages comprising an output stage configured to receive electrical energy from a power supply and an auxiliary path independent of the main signal path and comprising an output stage compensation circuit configured to generate a compensation current proportional to noise present in the power supply and apply the compensation current to cancel a power supply-induced current present in at least one of the feedback elements.

An operational amplifier and a differential amplifying circuit thereof. The differential amplifying circuit receives a differential input signal and outputs a differential output signal. The differential amplifying circuit includes an output port that has a first terminal and a second terminal, the differential output signal being outputted via the first and second terminals; a first transistor pair receiving the differential input signal via two first ends and coupling to the first and second terminals respectively via two second ends; a second transistor pair receiving the differential input signal via two first ends and coupling to the first and second terminals respectively via two second ends; and a third transistor pair receiving a control signal via two first ends and coupling to the first and second terminals respectively via two second ends. The control signal controls the third transistor pair to switch on or off and/or controls the current flowing therethrough.