There is provided a chopper stabilized amplifier with an input bias current reduced. The chopper stabilized amplifier includes a main amplifier and a correction circuit. The correction circuit includes a second gm amplifier of a full differential type. A first selector and the second gm amplifier are coupled to each other without DC blocking capacitors. The differential input state of the second gm amplifier is configured with a depletion-type transistor.

An amplifier circuit comprises a differential input stage configured to receive a differential input signal, wherein the differential input stage is susceptible to an offset error that includes a linear offset error portion and a nonlinear offset error portion; and an offset error correction circuit coupled to the differential input stage and configured to apply a second order error correction signal to the differential input stage to reduce the nonlinear portion of the offset error.

An electronic circuit comprises a primary amplifier circuit including a differential input and an output, an offset nulling amplifier circuit, and an impedance matching circuit. The offset nulling amplifier circuit includes a differential input and an output. The differential input of the primary amplifier circuit is operatively coupled to a differential input of the offset nulling amplifier circuit and the impedance matching circuit. The output of the offset nulling amplifier circuit is operatively coupled to the primary amplifier circuit and provides a voltage to reduce offset in an output signal of the primary amplifier circuit.

A gain stage includes an offset cancellation loop coupled to a first amplifier. The first amplifier has a first transfer function and a first gain, and the offset cancellation loop includes a second amplifier having a second transfer function and a second gain. The second transfer function is based on an inverse of the first transfer function and the second gain based on an inverse of the first gain. When the offset cancellation loop feeds back an output signal of the first amplifier to an input of the first amplifier, a high-pass pole (or high-pass corner frequency) of the first amplifier is maintained at a constant level in spite of variations in the gain of the first amplifier. In one case, the second amplifier in the offset cancellation loop may be a simpler and lower power version of the first amplifier.

A gain stage includes an offset cancellation loop coupled to a first amplifier. The first amplifier has a first transfer function and a first gain, and the offset cancellation loop includes a second amplifier having a second transfer function and a second gain. The second transfer function is based on an inverse of the first transfer function and the second gain based on an inverse of the first gain. When the offset cancellation loop feeds back an output signal of the first amplifier to an input of the first amplifier, a high-pass pole (or high-pass corner frequency) of the first amplifier is maintained at a constant level in spite of variations in the gain of the first amplifier. In one case, the second amplifier in the offset cancellation loop may be a simpler and lower power version of the first amplifier.

An electronic circuit comprises a primary amplifier circuit including a differential input and an output, an offset nulling amplifier circuit, and an impedance matching circuit. The offset nulling amplifier circuit includes a differential input and an output. The differential input of the primary amplifier circuit is operatively coupled to a differential input of the offset nulling amplifier circuit and the impedance matching circuit. The output of the offset nulling amplifier circuit is operatively coupled to the primary amplifier circuit and provides a voltage to reduce offset in an output signal of the primary amplifier circuit.

A high dynamic range sensing front-end for bio-signal recording systems in accordance with embodiments of the invention are disclosed. In one embodiment, a bio-signal amplifier includes an input signal, where the input signal is modulated to a predetermined chopping frequency, a first amplifier stage, a parallel-RC circuit connected to the first amplifier stage and configured to generate a parallel-RC circuit output by selectively blocking an offset current, a second amplifier stage connected to the parallel-RC circuit that includes a second input configured to receive the parallel-RC circuit output and generate a second output that is an amplified version of the input signal with ripple-rejection. Further, the bio-signal amplifier can also include an auxiliary path configured for boosting input impedance by pre-charging at least one input capacitor. In addition, the bio-signal amplifier can also include a DC-servo feedback loop that includes an integrator that utilizes a duty-cycled resistor.

A comparator offset calibration system having a comparator offset evaluator and a switched-capacitor network is disclosed, which is in an analog and digital dual domain structure. The comparator offset evaluator receives digital data from an analog-to-digital conversion module, evaluates an offset of a comparator of the analog-to-digital conversion module based on the received digital data, and outputs an evaluated result. The switched-capacitor network processes the evaluated result to generate a control signal. The analog-to-digital conversion module adjusts the offset of the comparator according to the control signal.

An amplifier includes a first input circuit, a second input circuit, a first compensation circuit, a second compensation circuit. The first input circuit changes a voltage level of the negative output node based on a first input signal. The second input circuit changes a voltage level of the positive output node based on a second input signal. The first compensation circuit changes the voltage level of the positive output node based on the first input signal. The second compensation circuit changes the voltage level of the negative output node based on the second output signal.

An amplification interface includes a drain of a first FET connected to a first node, a drain of a second FET connected to a second node, and sources of the first and second FETs connected to a third node. First and second bias-current generators are connected to the first and second nodes. A third FET is connected between the third node and a reference voltage. A regulation circuit drives the gate of the third FET to regulate the common mode of the voltage at the first node and the voltage at the second node to a desired value. A current generator applies a correction current to the first and/or second node. A differential current integrator has a first and second inputs connected to the second and first nodes. The integrator supplies a voltage representing the integral of the difference between the currents received at the second and first inputs.