A circuit includes a first amplifier having first and second inputs and first and second output, first and second input capacitors, a first feedback capacitor selectively coupled between the first input and the first output, and a second feedback capacitor selectively coupled between the second input and the second output. During a second phase of operation, the first and second feedback capacitors are decoupled from the output and the first amplifier is configured to sample an input common mode voltage, an output common mode voltage, and an input offset voltage of the first amplifier on the first and second input capacitors. During a first phase of operation, the first feedback capacitor is coupled between the input and the output, the second feedback capacitor is coupled between the input and the output, and the first amplifier is configured to amplify a differential input signal provided across the first and second inputs.

Provided are embodiments that include a circuit configured to operate in a disabled mode error reduction for high-voltage bilateral operational amplifier current source. The circuit includes an operational amplifier, and a switching circuit coupled to the operation amplifier, wherein the switching circuit is operable in a normal mode and a disabled mode, wherein the disabled mode reduces error current at the output of the operational amplifier. Also provided are embodiments for a method for operating a circuit in a disabled mode for error reduction.

There is provided a chopper stabilized amplifier with an input bias current reduced. The chopper stabilized amplifier includes a main amplifier and a correction circuit. The correction circuit includes a second gm amplifier of a full differential type. A first selector and the second gm amplifier are coupled to each other without DC blocking capacitors. The differential input state of the second gm amplifier is configured with a depletion-type transistor.

A sub-40 kilohertz low-frequency cutoff is provided for via a transimpedance amplifier comprising differential inputs and differential outputs; coupling capacitors comprising input terminals configured to receive electrical signals, and output terminals coupled to the differential inputs; and feedback paths coupled to the differential outputs and operable to level shift voltage levels at the input terminals. In some embodiments, the feedback paths comprise source follower transistors wherein the differential outputs are coupled to gate terminals of the source follower transistors or the feedback paths further comprise feedback resistors. In some embodiments, a bias resistor is coupled between the differential inputs.

An amplifier circuit comprises a differential input stage configured to receive a differential input signal, wherein the differential input stage is susceptible to an offset error that includes a linear offset error portion and a nonlinear offset error portion; and an offset error correction circuit coupled to the differential input stage and configured to apply a second order error correction signal to the differential input stage to reduce the nonlinear portion of the offset error.

A system includes an amplification circuit and offset calibration circuit. The amplification circuit includes a modulation circuit operable to modulate a received signal, an amplifier operable to amplify the modulated signal, and a modulation circuit operable to demodulate the amplified signal. The offset calibration circuit includes a logic circuit operable to set a control signal and adjust the control signal based on an output of the amplification circuit, where the output is based on the demodulated signal, and a compensation signal generator operable to generate a compensation signal based on the control signal to compensate for an offset associated with the amplification circuit, and apply the compensation signal on the amplification circuit to adjust the output of the amplification circuit. The offset calibration circuit in conjunction with the application circuit reduces flicker, offset, and offset drift, and also suppresses the upmodulate ripple due to chopping.

A semiconductor device in which variations are controlled is provided. The semiconductor device has a function of converting a digital signal into an analog signal, and includes a digital-analog converter circuit, an amplifier circuit, first to fourth switches, a first output terminal, a second output terminal, and a power source. The amplifier circuit is configured to perform feedback control when the first switch and the fourth switch are on and the second switch and the third switch are off. The amplifier circuit is configured to perform comparison control when the first switch and the fourth switch are off and the second switch and the third switch are on; utilizing this, variations in the digital-analog converter circuit and the amplifier circuit are controlled.

An electronic circuit comprises a primary amplifier circuit including a differential input and an output, an offset nulling amplifier circuit, and an impedance matching circuit. The offset nulling amplifier circuit includes a differential input and an output. The differential input of the primary amplifier circuit is operatively coupled to a differential input of the offset nulling amplifier circuit and the impedance matching circuit. The output of the offset nulling amplifier circuit is operatively coupled to the primary amplifier circuit and provides a voltage to reduce offset in an output signal of the primary amplifier circuit.

A gain stage includes an offset cancellation loop coupled to a first amplifier. The first amplifier has a first transfer function and a first gain, and the offset cancellation loop includes a second amplifier having a second transfer function and a second gain. The second transfer function is based on an inverse of the first transfer function and the second gain based on an inverse of the first gain. When the offset cancellation loop feeds back an output signal of the first amplifier to an input of the first amplifier, a high-pass pole (or high-pass corner frequency) of the first amplifier is maintained at a constant level in spite of variations in the gain of the first amplifier. In one case, the second amplifier in the offset cancellation loop may be a simpler and lower power version of the first amplifier.

A gain stage includes an offset cancellation loop coupled to a first amplifier. The first amplifier has a first transfer function and a first gain, and the offset cancellation loop includes a second amplifier having a second transfer function and a second gain. The second transfer function is based on an inverse of the first transfer function and the second gain based on an inverse of the first gain. When the offset cancellation loop feeds back an output signal of the first amplifier to an input of the first amplifier, a high-pass pole (or high-pass corner frequency) of the first amplifier is maintained at a constant level in spite of variations in the gain of the first amplifier. In one case, the second amplifier in the offset cancellation loop may be a simpler and lower power version of the first amplifier.