An integrated circuit device can include at least one input; at least one output configured to provide a multi-bit output value; at least one input; at least one output configured to provide a multi-bit output value; a plurality of configurable digital filter circuits; and switch circuits coupled to the at least one input and to the at least one output, the switch circuits configurable to connect same digital filter circuits as a single processing path or separate processing paths.

In a cascaded integrator comb (CIC) filter, a time-varying gain is added before the last integrating stage transforming its sub optimal boxcar impulse response into an FIR filter of arbitrary length. Make the coefficients sparse and taking them from a set of small integers leads to an efficient hardware implementation that does not compromise any of the essential CIC filter characteristics especially the overflow handling. The proposed sparse CIC structure can improve the worst case stop band attenuation by as much as 10 dB while occupying 77% of the chip area and consuming 30% less power compared to a standard a 5.sup.th order CIC filter, and reducing the overall bit growth of the filter and the amount of high rate operations. Design examples are given illustrating the advantages and flexibility of the proposed structure.

A digital filter includes integrator circuits configured to operate based on a clock of a sampling frequency f.sub.S that is equal to a sampling frequency of input data and determine a sum of the input data on a sample-by-sample basis, a frequency converter circuit configured to perform decimation on data of the sampling frequency f.sub.S to reduce the sampling frequency f.sub.S to a sampling frequency f.sub.D=f.sub.S/N, one or more differentiator circuits configured to operate based on a clock of the sampling frequency f.sub.D and subtract data of an immediately preceding sample from the input data, a differentiator circuit for removal of 50 Hz configured to operate based on the clock of the sampling frequency f.sub.D and subtract, from the input data, data preceding the input data by a plurality of samples, and a differentiator circuit for removal of 60 Hz configured to operate based on a clock of the sampling frequency f.sub.D and subtract, from the input data, data preceding the input data by a plurality of samples.

A digital frequency measuring apparatus includes a frequency divider dividing an input frequency signal and providing a divided frequency signal; a period counter counting clock cycles in a period of the divided frequency signal using a clock signal and providing a period count value for each period; and a digital filter amplifying the period count value using an accumulated gain, converting an amplified period count value into a frequency, and providing a first digital output value. The digital filter determines the accumulated gain using a predetermined stage number and a predetermined decimator factor.

A cascaded integrator-comb filter (CIC) that includes a differentiator, a rate changer, an integrator, and a multiplier. The differentiator is configured to differentiate an input signal to produce a differentiated input signal. The rate changer is coupled to the differentiator and is configured to interpolate the differentiated input signal based on an interpolation rate to produce an upsample signal. The integrator is coupled to the rate changer and is configured to integrate the upsample signal to produce an output signal. The multiplier is coupled to the differentiator, rate changer, and integrator and is configured to increase the output signal amplitude based on the interpolation rate.

Embodiments of the present disclosure include a method for designing the transfer function of efficient recursive FIR digital filters. The method is based on the cancellation of the poles of the transfer function of a multi-resonator sub-filter by zeros of the transfer function of a muti-stopper sub-filter. A compensator sub-filter can be applied for band shaping, is the method may be used to design low-pass, high-pass and band-pass filters, among other types. The FIR filters can be designed to have either a linear phase or a very nearly linear phase response. IIR filters with a nonlinear phase response can also be designed by the method of this invention. The method may additionally describe a digital circuit for the implementation of the transfer function of the invention.

A digital filter includes integrator circuits configured to operate based on a clock of a sampling frequency f.sub.S that is equal to a sampling frequency of input data and determine a sum of the input data on a sample-by-sample basis, a frequency converter circuit configured to perform decimation on data of the sampling frequency f.sub.S to reduce the sampling frequency f.sub.S to a sampling frequency f.sub.D=f.sub.S/N, one or more differentiator circuits configured to operate based on a clock of the sampling frequency f.sub.D and subtract data of an immediately preceding sample from the input data, a differentiator circuit for removal of 50 Hz configured to operate based on the clock of the sampling frequency f.sub.D and subtract, from the input data, data preceding the input data by a plurality of samples, and a differentiator circuit for removal of 60 Hz configured to operate based on a clock of the sampling frequency f.sub.D and subtract, from the input data, data preceding the input data by a plurality of samples.

The implementation of non-integer sample rate conversion and filtering of data sequences may be improved by performing both operations together with a system that includes a CIC filter and a control block that modifies internal states of the CIC filter. In one embodiment, input data samples provided at a first sample rate may be filtered by a CIC filter that includes a cascade of an integrating stage and a comb filter stage, each stage operating at a different sampling rate. A control block coupled to the CIC filter may modify at least one internal state of at least one of the integrating stage and comb filter stage of the CIC filter, wherein filtering by the CIC filter and modifying the at least one internal state causes the CIC filter to output data samples at a second sample rate unequal to the first sample rate.

The present invention relates to a digital interpolator, comprising an input to receive an input signal at a first clock frequency and comprising an output to provide an interpolated signal at a second clock frequency larger than the first clock frequency. The interpolator comprises a differentiator connected to the input, an interpolator stage connected to a differentiator output, and an integrator connected to the output and connected to an output of the interpolator stage.

An interleaved cascaded integrator-comb (CIC) filter receives an interleaved sensor output signal, including a plurality of digitized sensor signals at an input clock rate. An integrator of the interleaved CIC filter processes the interleaved signal to output an integrated interleaved signal. A downsampler of the interleaved CIC filter buffers portions of the integrated interleaved corresponding to a decimation rate for the interleaved signal. The portions of the signals are provided to a comb filter, which outputs a decimated interleaved signal.