An electronic filter comprising: a first coefficient circuit to provide a first coefficient-signal (coeff0) by applying coeff0=2*OSR1counter0, where OSR is the oversampling ratio, when a first counter-signal (counter0)>=OSR and applying coeff0=counter0+1, when counter0<OSR. The filter also comprises a first summation circuit to provide a first polarity-signal, polarity0, as either: coeff0 if the ADC bitstream signal is positive; or coeff0 if the ADC bitstream signal is negative; and integrate polarity0. The filter also comprises a counter modifier circuit to provide a second counter-signal, derived from counter0; a second coefficient circuit to provide a second coefficient-signal; and a second summation circuit to provide a second sub-filter signal. The filter also comprises an output logic circuit to provide a filter output signal to the filter output terminal, by switching between providing the first sub-filter signal and the second sub-filter signal as the filter output signal, at the frequency of a clock-signal.

In examples, a device includes a cascade of integrators (COI) filter including an accumulator having an output and a decimator having an input coupled to the output of the accumulator. An output of the decimator is an output of the COI filter. The device includes a SINC filter including the accumulator and the decimator of the COI filter. The SINC filter further includes a differentiator having an input coupled to the output of the decimator, in which an output of the differentiator is an output of the SINC filter. The device also includes a multiplexer having an output and first and second inputs. The first input of the multiplexer is coupled to the output of the COI filter, and the second input of the multiplexer is coupled to the output of the SINC filter.