A novel phase locked loop design utilizing novel phase-frequency detector, charge pump, loop filter and voltage controlled oscillator is disclosed. The phase-frequency detector includes a dual reset D-flip flop for use in multi-GHz phase locked loops. Traditional dead zone issues associated with phase frequency detector are improved/addressed by use with a charge transfer-based PLL charge pump.

An RF power amplifier includes a quadrature coupler, an in-phase amplifier, a quadrature amplifier, and a feed-forward signal path. The quadrature coupler includes an in-phase input node, a quadrature input node, an isolated node, and an RF signal output node. The in-phase amplifier includes an in-phase amplifier output node coupled to the in-phase input node. The quadrature amplifier includes a quadrature amplifier output node coupled to the quadrature input node. The feed-forward signal path is configured to couple and condition a signal from one of the in-phase amplifier and the quadrature amplifier in order to provide a feed-forward output signal that when provided at the feed-forward output node cancels one or more harmonic signals.

A ring oscillator includes: (i) one or more current sources each connected to a supply voltage source; and (ii) oscillation elements connected in series in a ring configuration each element including: (a) first and second input terminals; (b) first and second output terminals; (c) first and second inverters receiving input signals from the first and second input terminals, respectively, and providing output signals on the first and second output terminals, respectively; and (d) third and fourth inverters, each having an input terminal and an output terminal, wherein the input terminals of the third and fourth inverters are coupled to the first and second output terminals of the oscillator element, respectively, wherein the output terminals of third and fourth inverters are coupled to the second and first output terminals of the oscillator element, respectively, and wherein each of first, second, third and fourth inverters are coupled to the supply voltage source through the current sources.

Methods and apparatuses featuring a multiplying injection-locked oscillator are described. Some embodiments include a pulse-generator-and-injector and one or more injection-locked oscillators. The outputs of the pulse-generator-and-injector can be injected into corresponding injection points of an injection-locked oscillator. In embodiments that include multiple injection-locked oscillators, the outputs of each injection-locked oscillator can be injected into the corresponding injection points of the next injection-locked oscillator. Some embodiments reduce deterministic jitter by dynamically modifying the loop length of an injection-locked oscillator, and/or by using a duty cycle corrector, and/or by multiplexing/blending the outputs from multiple delay elements of an injection-locked oscillator.

The disclosure of the present application presents a multiple-ring coupled ring oscillator design that employs multiple-ring coupling to achieve improved phase noise by minimizing noise injection from tail current and adjacent rings, while providing additional output phases for multiphase signal generation. In one non-limiting exemplary prototype embodiment, a 1.5 GHz triple-ring coupled ring oscillator achieved measured phase noise of 110.5 dBc/Hz at 1 MHz offset, demonstrating phase noise reduction of 7 dB compared with its single-ring oscillator counterpart. The MROs couple multiple rings with proper phase shifting to achieve improved phase noise. Common source coupling benefits from tail current noise reduction, and introducing phase delays in the coupling paths minimizes noise coupling from the adjacent cores. The overall effect leads to improved phase noise performance as demonstrated in quadrature voltage controlled VCO designs. The concept is applied to ring oscillator designs and, as stated previously, demonstrates a triple-ring coupled ring oscillator with phase noise improvement. The design of the present application also triples the number of output phases compared to its single ring oscillator counterpart. The application of injection-locked PLL by using proposed multiple ring coupled ring oscillator achieves the same low phase noise as traditional IL-PLL does while lowering the reference spur at auxiliary ring's output. In another non-limiting exemplary embodiment, the proposed IL-PLL consumes 13.5 mW of power, while achieving in-band phase noise of 120.97 dBc/Hz at 1 MHz offset at 1.1 GHz output frequency.

In order to prevent or at least reduce parasitic capacitive loads at a device (200) for controllably delaying an electrical signal, the device comprising a first signal transfer path (207) between a signal input (201) and a signal output (204), the first signal transfer path (207) comprising a first signal transfer stage (208) with a first differential pair (209) and a common, adjustable first quiescent current source (212), a second signal transfer path (213) between the signal input (201) and the signal output (204), the second signal transfer path (213) comprising a second signal transfer stage (214) with a second differential pair (215) and a common, adjustable second quiescent current source (218), and an internal delay stage (219), arranged between the signal input (201) and the second signal transfer stage (214) and having a third differential pair (220) and a common, adjustable third quiescent current source (223), and a signal combination stage (224) for additively superimposing the electrical signal transferred via the first signal transfer path (207) on to the electrical signal transferred via the second signal transfer path (213),
at least one current modulation stage (235, 236) for adjusting the quiescent current of at least one of the first and/or second and/or third quiescent current source (212, 218, 223) is proposed.

A corresponding method for controlling the delay of an electrical signal and for said delaying the electrical signal is also proposed.

A ring voltage control oscillator includes: a conversion unit (100), cascaded multistage delay units (200) and cascaded multistage isolation buffer units (300). The conversion unit (100) receives a voltage signal controlled by the external, converts the voltage signal into a current signal and respectively transmits the current signal to a plurality of delay units (200) and a plurality of isolation buffer units (300). The delay unit (200) comprises two signal input terminals and two signal output terminals; the isolation buffer unit (300) comprises two signal input terminals and two signal output terminals; a first signal input terminal and a second signal input terminal of the isolation buffer unit (300) are correspondingly connected to a first signal output terminal and a second signal output terminal of the same stage of the delay unit (200), respectively; clock signals outputted by first signal output terminals of two adjacent stages of the isolation buffering units (300) have the same phase difference; clock signals outputted by the second signal output terminals of two adjacent stages of the isolation buffering units (300) have the same phase difference.

The present invention relates to passive phased injection locked circuit and ring-based voltage controlled oscillators. A passive phased injection locked circuit comprises first and second transmission lines, each has a plurality of discrete elements, that are operative to delay the phase of AC signal. Between the first and second transmission lines, a capacitor network is formed to advance the phases of the AC signal in concert along the transmission lines. For the ring-based voltage controlled oscillators, each of the first and second transmission lines has an odd number of discrete elements.

Clock generation from an external reference by generating a reference clock gating signal using a reference clock gating circuit; enabling a ring-oscillator-injection mode using the reference clock gating signal to disable a first buffer of a ring oscillator and to enable a reference clock injection buffer, the first buffer and the injection buffer having parallel connected outputs that connect to a next buffer input; receiving a reference clock transition of a reference clock signal at the injection buffer and injecting it into the next buffer; and enabling a ring-oscillator-closed-loop mode by using the reference clock gating signal to enable the first buffer and to disable the reference clock injection buffer.

Disclosed is a wide band frequency oscillator circuit and oscillation method using a ring voltage-controlled oscillator (VCO). The frequency oscillator circuit includes a low drop-out (LDO) regulator configured to generate an input voltage of a ring VCO, and the ring VCO connected to the LDO regulator and configured to control an oscillation frequency based on the input voltage, wherein the LDO regulator includes a feedback adjustable resistor.