The present technology includes a replica circuit and an oscillator including the same. The replica circuit includes a first terminal to which a replica voltage having a positive voltage is supplied, a second terminal to which a ground voltage is supplied, a replica main circuit connected between the first terminal and the second terminal and configured to form a first current path in response to a voltage of the first terminal, and a replica sub circuit connected in parallel with the replica main circuit between the first terminal and the second terminal and configured to form a second current path in response to the voltage of the first terminal. A current flowing through the second current path having a replica sub current amount is less than a current flowing through the first current path having a replica main current amount.

An apparatus comprising a local oscillator (LO) for driving a mixer, the LO being configured to oscillate at an oscillation frequency, and generate a first set of LO signals, wherein each of the first set of LO signals has a LO signal frequency equal to a first multiplication factor m multiplied by the oscillation frequency, the first multiplication factor m, being an integer greater than or equal to two, and each of the first set of LO signals is separated by adjacent LO signals by a phase difference equal to 360° divided by a first variable n, the first variable n being an integer that is greater than or equal to two.

A novel phase locked loop design utilizing novel phase-frequency detector, charge pump, loop filter and voltage controlled oscillator is disclosed. The phase-frequency detector includes a dual reset D-flip flop for use in multi-GHz phase locked loops. Traditional dead zone issues associated with phase frequency detector are improved/addressed by use with a charge transfer-based PLL charge pump.

An injection-locked oscillator includes an oscillator and an injection circuit. The oscillator includes a first oscillation node through which a first oscillation signal is output and a second oscillation node through which a second oscillation signal is output, the second oscillation signal having a phase opposite to that of the first oscillation signal. The injection circuit provides an injection current between the first oscillation node and the second oscillation node according to a reference signal. The injection circuit includes a charging element configured to be charged or discharged in response to a reference signal and to provide the injection current between the first oscillation node and the second oscillation node.

A time delay circuit comprising a plurality of differential delay cells each having a respective time delay and being arranged in series. Each delay cell comprises first and second inverter sub-cells, each comprising a respective PMOS transistor and an NMOS transistor arranged in series such that their respective drain terminals are connected at a drain node. Each of the transistors has a back-gate terminal and is arranged such that a respective voltage applied to said back-gate terminal linearly controls its respective threshold voltage. The back-gate terminal of the PMOS transistor in each inverter sub-cell is connected to the drain node of the other sub-cell and/or the back-gate terminal of the NMOS transistor in each inverter sub-cell is connected to the drain node of the other sub-cell. A control signal varies the time delay of the delay cell by adjusting a voltage supplied to a back-gate terminal of a transistor.

Systems and methods are disclosed for wide frequency range voltage controlled oscillators. For example, an apparatus includes a Voltage Controlled Oscillator (VCO) including a delay cell which includes first and second current sources provided in parallel with one another. The first current source is controlled by a voltage control input connected to a voltage control terminal and the second current source is controlled by a bias voltage input connected to a bias voltage terminal. The first current source provides an alternate current path in the delay cell when the second current source is off. The delay cell is operable to receive an input and produce an output using the alternate current path.

Apparatus and methods for rotary traveling wave oscillators (RTWOs) are disclosed. In certain embodiments, an RTWO system include an RTWO ring that carries a traveling wave, a plurality of selectable capacitors distributed around the RTWO ring and each operable in a selected state and an unselected state, and a decoder system that controls selection of the plurality of selectable capacitors based on a frequency tuning code. The frequency tuning code includes a fine tuning code and a coarse tuning code, and the decoder system is operable to maintain a constant number of capacitors that toggle state for each value of the fine tuning code.

The present disclosure relates to a ring-oscillator with glitch-free frequency-tuning. The disclosed ring-oscillator at least includes multiple delay stages coupled in series within a ring loop and having a first delay stage, a capacitor bank coupled between an output of the first delay stage and ground, and a timing block configured to receive an output signal of the first delay stage and at least one controlling signal. The at least one controlling signal determines at least one capacitor in the capacitor bank connecting or disconnecting to the ring loop. The timing block is configured to pass or not pass the at least one controlling signal to the capacitor bank based on whether the output signal of the first delay stage meets a certain condition. Therefore, the connection or disconnection of the at least one capacitor does not cause a significant voltage change at the output of the first delay stage.

The phase-lock loop (PLL) can include a variable frequency oscillator adjustable to control the phase of the output signal; a primary control subsystem including a phase detector and a connection between the output signal and the phase detector, the phase detector generating a primary control signal to adjust the variable frequency oscillator; and a secondary control subsystem having an analog-to-digital converter and a digital-to-analog converter connected in series to receive the primary control signal and generate a secondary control signal also connected to independently adjust the variable frequency oscillator.

A signal may be arbitrarily delayed in discrete steps by an arbitrary delay buffer having an analog delay and a digital delay. An analog delay may have a number of selectable delay stages (e.g. ring oscillator with VCDL stages). A digital delay may have rising and falling edge detectors, resettable ring oscillators that oscillate in response to rising or falling edges and counters to count oscillations and generate rising and falling edge delay signals when oscillation counts reach rising and falling edge delay counts. A resettable ring oscillator may have a resettable stage (e.g. VCDL) that may be enabled and disabled. Selection of one or both digital and analog delays and respective delay times may be based on one or more characteristics. For example, an analog delay may delay an input signal or a delayed input signal received from the digital delay based on input signal frequency or total delay.