Patent classifications
H03K3/29
Ternary digit logic circuit
A ternary logic circuit according to the present invention includes a pull-up device (100) and a pull-down device (200) connected in series between power voltage sources (V.sub.DD and GND), and an input voltage (V.sub.IN) source and output voltage (V.sub.OUT) source. When both the pull-up device (100) and the pull-down device (200) are turned off by an input voltage (V.sub.IN), both the pull-up device (100) and the pull-down device (200) operate as simple resistors which are affected only by an output voltage (V.sub.OUT) and form a ternary digit (1 state) through voltage division. When only one of the pull-up device (100) or the pull-down device (200) is turned on to allow a current to flow therethrough, V.sub.DD (2 state) or GND (0 state) is output as the output voltage (V.sub.OUT). Accordingly, a bit density can be remarkably increased.