A flip flop standard cell that includes a data input terminal configured to receive a data signal, clock input terminal configured to receive a clock signal, a data output terminal, and a latch. A bit write circuit is configured to receive a bit write signal. The received data signal is latched and provided at the output terminal in response to the bit write signal and the clock signal. A hold circuit is configured to receive a hold signal, and the received data signal is not latched and provided at the data output terminal in response to the hold signal and the clock signal.

The invention provides a dynamic D flip-flop, and a data operation unit, a chip, a hash board and a computing device using the same. The dynamic D flip-flop comprises: an input terminal, an output terminal and at least one clock signal terminal; a first latch unit for transmitting data of the input terminal and latching the data under control of a clock signal; a second latch unit for latching data of the output terminal and inversely transmitting the data latched by the first latch unit under control of a clock signal; and an output driving unit for inverting and outputting the data received from the second latch unit; wherein the second latch unit outputs in high level, low level and high impedance states by means of a single element under control of a clock signal. Therefore, the invention can effectively reduce chip area, power consumption, and logic delay.

A flip flop standard cell that includes a data input terminal configured to receive a data signal, clock input terminal configured to receive a clock signal, a data output terminal, and a latch. A bit write circuit is configured to receive a bit write signal. The received data signal is latched and provided at the output terminal in response to the bit write signal and the clock signal. A hold circuit is configured to receive a hold signal, and the received data signal is not latched and provided at the data output terminal in response to the hold signal and the clock signal.

A hybrid fin flip flop circuit may comprise a mixture of 1-fin transistors and multi-fin transistors. In one example, a flip flop circuit may comprise 1-fin transistors in at least one of the critical paths of the flip flop circuit such as the drive circuit, the input circuit, or the output circuit. In one example, a flip flop circuit may include: an input circuit; a clock driver circuit; an output circuit; and a latch circuit; wherein one of the input circuit, the clock driver circuit, or the output circuit comprises a multi-fin transistor and the latch circuit comprises a plurality of 1-fin transistors.

Embodiments of the disclosure provide a circuit structure and related method to provide a radiation resistant memory cell. A circuit structure may include a first latch having an input node and an output node. A second latch has an input node and an output node, in which the output node of the second latch is coupled to the input node of the first latch, and the input node of the second latch is coupled to the output node of the first latch. A read/write (R/W) circuit includes a plurality of transistors coupling a word line, a bit line, and an inverted bit line to at least two outputs. One of the at least two outputs is coupled to the input node of the first latch and another of the outputs is coupled to the input node of the second latch.

A first flipflop outputs a first signal synchronized with a first clock signal, a second flipflop outputs a second signal synchronized with a second clock signal, and a third flipflop outputs a third signal synchronized with a third clock signal. The second flipflop includes first to fifth transistors. In the first transistor, the second clock signal is input to a first terminal and the second signal is output from a second terminal. In the second transistor, a first signal is input to a first terminal, a second terminal is electrically connected to a gate of the first transistor, and the first clock signal is input to a gate. In the third transistor, the third signal is input to a first terminal, a second terminal is electrically connected to the gate of the first transistor, and the third clock signal is input to a gate.

A first flipflop outputs a first signal synchronized with a first clock signal, a second flipflop outputs a second signal synchronized with a second clock signal, and a third flipflop outputs a third signal synchronized with a third clock signal. The second flipflop includes first to fifth transistors. In the first transistor, the second clock signal is input to a first terminal and the second signal is output from a second terminal. In the second transistor, a first signal is input to a first terminal, a second terminal is electrically connected to a gate of the first transistor, and the first clock signal is input to a gate. In the third transistor, the third signal is input to a first terminal, a second terminal is electrically connected to the gate of the first transistor, and the third clock signal is input to a gate.

An example gate driver for an array of sensing pixels is disclosed. The gate driver includes a first flip-flop including a first data input and a first data output. The first data output is coupled to a first group of sensing pixels of the array. The gate driver also includes a second flip-flop including a second data input and a second data output. The second data output is coupled to a second group of sensing pixels of the array. The gate driver further includes a first insertion circuit configured to receive a first start signal and to cause, based on the first start signal, the second flip-flop to drive the second group of sensing pixels without the first flip-flop driving the first group of sensing pixels for a scan of the array.

A semiconductor device may include an amplification circuit. The amplification circuit may be configured to generate an output signal and an output bar signal based on a mode signal, first and second control signals, an input signal, and an input bar signal. The amplification circuit may determine voltage levels of the output signal and the output bar signal based on the mode signal and the first and second control signals regardless of the input signal and the input bar signal.

A flip flop standard cell that includes a data input terminal configured to receive a data signal, clock input terminal configured to receive a clock signal, a data output terminal, and a latch. A bit write circuit is configured to receive a bit write signal. The received data signal is latched and provided at the output terminal in response to the bit write signal and the clock signal. A hold circuit is configured to receive a hold signal, and the received data signal is not latched and provided at the data output terminal in response to the hold signal and the clock signal.