A multi-chip package includes: a first semiconductor integrated-circuit (IC) chip; a second semiconductor integrated-circuit (IC) chip over and bonded to the first semiconductor integrated-circuit (IC) chip; a plurality of first metal posts over and coupling to the first semiconductor integrated-circuit (IC) chip, wherein the plurality of first metal posts are in a space beyond and extending from a sidewall of the second semiconductor integrated-circuit (IC) chip; and a first polymer layer over the first semiconductor integrated-circuit (IC) chip and in the space, wherein the plurality of first metal posts are in the first polymer layer, wherein a top surface of the first polymer layer, a top surface of the second semiconductor integrated-circuit (IC) chip and a top surface of each of the plurality of first metal posts are coplanar.

A level shifter circuitry is provided. The level shifter circuitry includes a first sub-circuit connected to a first power supply voltage, a second sub-circuit connected to a second power supply voltage and a shifting circuit which is connected to the first and second sub-circuits and outputs the first power supply voltage or the second power supply voltage to an output terminal or an inverted output terminal in response to a signal applied to an input node in accordance with an enable signal.

Various implementations described herein are related to a device having a level shifting circuit that shifts an input voltage in a first domain to an output voltage in a second domain, and also, the level shifting circuit may shift the input voltage to the output voltage based on a first level shifting response. The device may also include a boost circuit that increases the input voltage and provides a boosted input voltage to the level shifting circuit so that the level shifting circuit shifts the input voltage to the output voltage based on the boosted input voltage.

Examples disclosed herein relate to set-reset (SR) latch circuits and methods for manufacturing the same. In some of the disclosed examples, a SR latch circuit includes an inverter storage loop for storing state information and a set of p-channel field-effect transistors (PFETs) for control circuitry. The PFETs may include first and second PFETs connected to a first node of the inverter storage loop, and third and fourth PFETs connected to a second node of the inverter storage loop. Gate terminals of the first and fourth PFETs may be connected to a first control input, and gate terminals of the second and third PFETs may be connected to a second control input.

A voltage level shifter device an input stage and an output stage. The input stage is configured to lower one of the first and second output terminals to the low level according to the level of the input voltage. A latch circuit includes a first branch having a first PMOS transistor and a second PMOS transistor coupled in series coupled between a shifted-high-level voltage supply terminal and the first output terminal and a second branch having a third PMOS transistor an a fourth PMOS transistor coupled in series between the shifted-high-level voltage supply terminal and the second output terminal. The first output terminal is a gate of the second PMOS transistor and to a gate of the third PMOS transistor. The second output terminal is coupled a gate of the fourth PMOS transistor and to a gate of the first PMOS transistor.

A DC-DC converter converts voltage from a battery source providing a voltage V.sub.in to a lower level. A four-level transistor stack selectively connects an input voltage and flying capacitor voltages to an output inductor. Stress reduction transistors limit the charging of the flying capacitors to V.sub.in/3. The stress reduction transistors can also limit switching transistor voltages to V.sub.in/3. Freewheel switches can be used to limit ringing in the output inductor.

A level shifter circuit shifts a digital signal between first and second voltage levels. For a LOW to HIGH transition, an output PMOS transistor is switched on using a first NMOS transistor activated by the digital signal at the first voltage level while a second NMOS transistor is switched off to uncouple the output PMOS transistor from ground, and a third NMOS transistor is switched off to uncouple a current mirror circuit from ground. For a HIGH to LOW transition, the output PMOS transistor is switched off and a fourth NMOS transistor is switched on using an output of the current mirror circuit. The second NMOS transistor is switched on using an inverted version of the digital signal, and the current in the current mirror circuit is turned off with a fifth NMOS transistor when the drain of the output PMOS transistor approaches the voltage level of ground.

A level shifter with high reliability is shown, which has a power multiplexer receiving a plurality of power voltage candidates to selectively output a selected power voltage. In response to a low-to-high transition of the input signal of the level shifter, the first output terminal of the level shifter is pulled up to the selected power voltage by the second pull-up device, and the first pull-down device pulls down the second output terminal of the level shifter to a low-voltage level corresponding to the selected power voltage. In response to a high-to-low transition of the input signal, the second output terminal of the level shifter is pulled up to the selected power voltage by the first pull-up device, and the second pull-down device pulls down the first output terminal of the level shifter to the low-voltage level corresponding to the selected power voltage.

An integrated circuit may include a clock gating cell based. The clock gating cell may include a first 2-input logic gate configured to receive a clock input and a first signal and generate a second signal, an inverter configured to receive the second signal and generate a clock output, and a 3-input logic gate including a second 2-input logic gate configured to generate the first signal. The first 2-input logic gate and the second 2-input logic gate form a set reset (SR) latch by being cross-coupled, the 3-input logic gate includes a feedback transistor configured to exclusively receive an internal signal of the first 2-input logic gate, and an activation of the feedback transistor by the internal signal is configured to avoid a race condition by preventing a pull-up or a pull-down of a first node at which the first signal is generated.

A level shifting circuit includes negative voltage shifting circuitry including a first leg and a second leg. The first leg includes a first plurality of NMOS transistors in series with a first input node and a negative amplified voltage, and the second leg includes a second plurality of NMOS transistors in series with a second input node and the negative amplified voltage. The level shifting circuit further includes positive voltage shifting circuitry including a first plurality of high voltage transistors in series with a positive amplified voltage and an output node of the level shifting circuit, and a second plurality of high voltage transistors in series with a first intermediate node of the first leg of the negative voltage shifting circuitry and the output node of the level shifting circuit. The level shifting circuitry further includes input circuitry including a plurality of inverters.