A high-voltage level shift circuit includes: a first high withstand voltage NMOS transistor driven by an on command; a second high withstand voltage NMOS transistor driven by an off command; a first PMOS current mirror circuit inputting a drain current of the first high withstand voltage NMOS transistor to a reference side; a second PMOS current mirror circuit inputting a drain current of the second high withstand voltage NMOS transistor to a reference side; a first NMOS current mirror circuit inputting an output current of the second PMOS current mirror circuit to a reference side; and an I/V signal conversion circuit receiving an output of the first PMOS current mirror circuit and an output of the first NMOS current mirror circuit to obtain an output control voltage signal.

Stacked voltage domain level shifting circuits for shifting signals low-to-high or high-to-low include a storage cell powered by a mid-range supply rail of the stacked voltage domain level shifting circuit, and control drivers powered by moving supply voltages generated by the storage cell, wherein the control drivers coupled to drive gates of common-source configured devices coupled to storage nodes of the storage cell.

A level shift circuit includes first and second NMOS transistors that are coupled between a first supply terminal, and first and second output nodes, respectively, and have respective control terminals receiving input signals of a low amplitude, third and fourth PMOS transistors which are coupled between a second supply terminal, and the first and second output nodes outputting signals of high amplitude, respectively, a fifth PMOS transistor which is coupled between a gate of the third PMOS transistor and the second output node, and has a gate coupled to the first output node, a sixth PMOS transistor which is coupled between a gate of the fourth PMOS transistor and the first output node, and has a gate coupled to the second output node, and first and second load elements which are coupled between the second supply terminal and the gates of the third and fourth PMOS transistors, respectively.

A high voltage level shifting circuit and related semiconductor devices are presented. The circuit comprises: a level conversion circuit that converts an input signal with a first high voltage to an output signal with a second high voltage; a first switch having a first node connected to a first power source and a second node connected to a control node of a first transistor; a second switch having a first node connected to the control node of the first transistor and a second node connected to a first connection node; and a switch control circuit connected to the first switch and the second switch and controls them not to be close at the same time. By adding these two switches to the level conversion circuit, this inventive concept substantially lowers the static current generated during a high voltage level conversion process.

A high-voltage level shift circuit includes: a first high withstand voltage NMOS transistor driven by an on command; a second high withstand voltage NMOS transistor driven by an off command; a first PMOS current mirror circuit inputting a drain current of the first high withstand voltage NMOS transistor to a reference side; a second PMOS current mirror circuit inputting a drain current of the second high withstand voltage NMOS transistor to a reference side; a first NMOS current mirror circuit inputting an output current of the second PMOS current mirror circuit to a reference side; and an I/V signal conversion circuit receiving an output of the first PMOS current mirror circuit and an output of the first NMOS current mirror circuit to obtain an output control voltage signal.

A flip-flop includes a pulse-generator and a pulse-controlled latch. The pulse generator includes a first inverter to invert a clock signal, a second inverter to invert the inverted clock signal to generate a delayed clock signal, and a NOR gate having a first input coupled to an output of the first inverter, a second input coupled to the output of the second inverter, and an output, which, in operation, provides a pulse signal in response to a rising edge of a received clock signal. The pulse-controlled latch circuit has a data input and is controlled by the pulse signal and the delayed clock signal. The flip-flop may include a multiplexer to select an input signal.

A level shifter includes an input circuit having first and second input terminals configured to receive complementary input signals at a first voltage level and a second voltage level. A cross-latch circuit is coupled to the input circuit, and has first and second output terminals configured to provide complementary output signals at a third voltage level and a fourth voltage level. The input circuit includes first and second control nodes configured to output first and second control signals at the first voltage level and the fourth voltage level based on the input signals. A tracking circuit is coupled to the input circuit and the cross-latch circuit, and is configured to input first and second tracking signals to the cross-latch circuit based on the first and second control signals, wherein the first tracking signal is the greater of the first control signal and the third voltage level, and the second tracking signal is the greater of the second control signal and the third voltage level.

A flip-flop includes a pulse-generator and a pulse-controlled latch. The pulse generator includes a first inverter to invert a clock signal, a second inverter to invert the inverted clock signal to generate a delayed clock signal, and a NOR gate having a first input coupled to an output of the first inverter, a second input coupled to the output of the second inverter, and an output, which, in operation, provides a pulse signal in response to a rising edge of a received clock signal. The pulse-controlled latch circuit has a data input and is controlled by the pulse signal and the delayed clock signal. The flip-flop may include a multiplexer to select an input signal.

The present technology relates to a power source monitoring circuit, a power on reset circuit, and a semiconductor device that are capable of reducing a steady-state current. The semiconductor device includes a level shifter circuit that performs level conversion on a digital signal output from a predetermined block and outputs a resultant signal to another block that operates by a power source different from the power source of the predetermined block, and a power source monitoring circuit that controls an operation of the level shifter circuit. The power source monitoring circuit stops an operation of the level shifter circuit on the basis of a status of the power source that supplies power to the predetermined block and a standby control signal for controlling an operation status of the other block. Further, the power source monitoring circuit is provided with a transistor on a path of a steady-state current, and the steady-state current is inhibited from flowing in accordance with the standby control signal. The present technology can be applied to a semiconductor device.

The present invention provides a level shift circuit and a semiconductor device capable of extending a power supply potential range in which the level shift operation can be performed.

A level shift circuit includes amplitude amplifying circuits AMPt1, AMPb1, and a sublevel shift circuit SLSC1. The amplitude amplifying circuits AMPt1, AMPb1 are supplied with a reference power supply potential GND and an external power supply potential VDD2 and, in response to an input signal (INT, INB) of an internal power supply voltage amplitude (VDD1 (<VDD2) amplitude), output signals SND1, SND2 with an amplitude larger than the VDD1 amplitude and smaller than the external power supply voltage amplitude (VDD2 amplitude). The sublevel shift circuit SLSC1 is supplied with the reference power supply potential GND and the external power supply potential VDD2, and outputs an output signal (OUT, OUTB) of the VDD2 amplitude in response to the signals SND1, SND2.