A semiconductor device includes a setting circuit and a reset circuit. The setting circuit includes a latch circuit having first and second inverters driven by a first power voltage whose level is fixed and a first transistor which is switched between an ON state and an OFF state on the basis of a level of a second power voltage whose level varies depending on a surrounding environment, and sets data corresponding to a reference voltage to the latch circuit in response to the first transistor being switched to the ON state. The reset circuit includes an N-type second transistor connected to an output of the first inverter and an input of the second inverter. The second transistor sets data corresponding to the reference voltage to the latch circuit in response to the second voltage being equal to or lower than a predetermined voltage value.

A level shift circuit includes first and second NMOS transistors that are coupled between a first supply terminal, and first and second output nodes, respectively, and have respective control terminals receiving input signals of a low amplitude, third and fourth PMOS transistors which are coupled between a second supply terminal, and the first and second output nodes outputting signals of high amplitude, respectively, a fifth PMOS transistor which is coupled between a gate of the third PMOS transistor and the second output node, and has a gate coupled to the first output node, a sixth PMOS transistor which is coupled between a gate of the fourth PMOS transistor and the first output node, and has a gate coupled to the second output node, and first and second load elements which are coupled between the second supply terminal and the gates of the third and fourth PMOS transistors, respectively.

A level conversion circuit includes: first P-ch and N-ch transistors and second P-ch and N-ch transistors respectively connected in series between first and second power sources; third and fourth P-ch transistors respectively connected between the gates of the second and first P-ch transistors and the drain of the first and second P-ch transistors; and fifth and sixth P-ch transistors respectively connected between the gates of the second and first P-ch transistors and a third power source, wherein differential input signals are applied to the gates of the first and second N-ch transistors, a bias voltage is applied to the gates of the third and fourth P-ch transistors, the gate of the fifth and sixth P-ch transistors are respectively connected to connection nodes of the first P-ch and N-ch transistors the second P-ch and N-ch transistors.

According to one general aspect, an apparatus may include a latch, and a control circuit. The latch may receive an input enable signal and generate a latched enable signal. The latch may also pass the input enable signal to the latched enable signal when the latch is transparent. The control circuit may be electrically coupled to the latch. The control circuit may receive as input an ungated clock signal, and generate a gated clock signal and a latch control signal. The latch control signal may be configured to make the latch transparent when the ungated clock signal is in a predefined state and when one of the input enable signal and the latched enable signal are in an enabled state. The control circuit may be configured to pass the ungated clock signal to the gated clock signal when the latched enable signal is in the enabled state.

According to one general aspect, an apparatus may include a latch, and a control circuit. The latch may receive an input enable signal and generate a latched enable signal. The latch may also pass the input enable signal to the latched enable signal when the latch is transparent. The control circuit may be electrically coupled to the latch. The control circuit may receive as input an ungated clock signal, and generate a gated clock signal and a latch control signal. The latch control signal may be configured to make the latch transparent when the ungated clock signal is in a predefined state and when one of the input enable signal and the latched enable signal are in an enabled state. The control circuit may be configured to pass the ungated clock signal to the gated clock signal when the latched enable signal is in the enabled state.

A voltage level shifter may include a first input unit, a second input unit, a first mirror unit, a second mirror unit, and a clamping block. The first and second input units may receive a first input signal and a second input signal, respectively, and form current paths of a negative output node and a positive output node. The first and second mirror units may provide a first voltage to the negative output node and the positive output node. The clamping block may receive a second voltage, and couple the positive output node and the negative output node with the first and second mirror units, respectively.

A semiconductor device includes a setting circuit and a reset circuit. The setting circuit includes a latch circuit having first and second inverters driven by a first power voltage whose level is fixed and a first transistor which is switched between an ON state and an OFF state on the basis of a level of a second power voltage whose level varies depending on a surrounding environment, and sets data corresponding to a reference voltage to the latch circuit in response to the first transistor being switched to the ON state. The reset circuit includes an N-type second transistor connected to an output of the first inverter and an input of the second inverter. The second transistor sets data corresponding to the reference voltage to the latch circuit in response to the second voltage being equal to or lower than a predetermined voltage value.

A voltage level shifter may include a first input unit, a second input unit, a first mirror unit, a second mirror unit, and a clamping block. The first and second input units may receive a first input signal and a second input signal, respectively, and form current paths of a negative output node and a positive output node. The first and second mirror units may provide a first voltage to the negative output node and the positive output node. The clamping block may receive a second voltage, and couple the positive output node and the negative output node with the first and second mirror units, respectively.

A level conversion circuit includes: first P-ch and N-ch transistors and second P-ch and N-ch transistors respectively connected in series between first and second power sources; third and fourth P-ch transistors respectively connected between the gates of the second and first P-ch transistors and the drain of the first and second P-ch transistors; and fifth and sixth P-ch transistors respectively connected between the gates of the second and first P-ch transistors and a third power source, wherein differential input signals are applied to the gates of the first and second N-ch transistors, a bias voltage is applied to the gates of the third and fourth P-ch transistors, the gate of the fifth and sixth P-ch transistors are respectively connected to connection nodes of the first P-ch and N-ch transistors the second P-ch and N-ch transistors.

A low-voltage to high-voltage level shifter circuit includes an input circuit, a voltage shifting circuit, and an output circuit. The input circuit is configured to receive an input signal having a voltage range between a first voltage and a ground voltage, and to provide an inverted input signal and a delayed version of the inverted input signal. The voltage shifting circuit is coupled to the input circuit and is configured to receive the input signal, the inverted input signal, and the delayed version of the inverted input signal. The voltage shifting circuit is configured to provide an internal signal having a voltage range between a second voltage and the ground voltage, the second voltage being higher than the first voltage. The output circuit provides an output voltage in the high-voltage range for the corresponding input voltage in the low-voltage range.