A computer-implemented method for designing an integrated circuit includes; performing a simulation on input data or an initial layout to determine whether or not a design constraint has been violated. Upon determining that the design constraint has been violated, creating a redesign layout by adding a cutting area without changing the size of the integrated circuit. The adding of the cutting area separates at least one of an active region and a gate line. At least one of the initial layout and redesign layout is stored in a computer readable storage medium.

A receiver includes a first transfer gate, a first inverter, a second inverter, a second transfer gate, a third inverter, and a fourth inverter connected in series, a first power supply supplying power to the first and second inverters, a second power supply supplying power to the third and fourth inverters, a third power supply supplying power to the second transfer gate, first and second signals having opposite logic levels for controlling the first transfer gate. The third power supply is significantly lower than the first or second power supply. The leakage current of the receiver is significantly reduced in the core when the second power supply remains on but the first power supply is turned off while the performance of the receiver remains the same.

Multi-bit data flip-flops are disclosed that provide bit initialization through propagation of scan bits. Input multiplexers are configured to select between input data bits and input scan bits based upon mode select signals. Master latches receive and latch outputs from the input multiplexers. Slave latches receive and latch outputs from the master latches and also provide propagated input scan bits to the input multiplexers. A first state for the mode select signals selects the input data bits for a data mode of operation, and a second state for the mode select signals selects the input scan bits for a scan mode of operation. Further, the input multiplexers, master latches, and slave latches are configured to operate in an initialization mode to pass a fixed input scan bit through the multi-bit data flip-flop based upon initialization signals (e.g., set and/or reset signals).

A device includes a master latch, a slave latch and a retention latch coupled to each other. The retention latch includes first and second active areas, first and second gate structures. The first and second active areas extend in a first direction. The first gate structure extends in a second direction, the first gate structure including first and second portions that are separated from each other. The first portion is arranged over the first active area, and the second portion is arranged over the second active area. The second gate structure extends in the second direction, and is arranged over the first active area. The second gate structure is separated from the second active area and the first gate structure in a layout view. An end portion of the second active area is between the first gate structure and the second gate structure.

In one example, the apparatus includes a first AND gate, a second AND gate, a first NOR gate, a second NOR gate, a third NOR gate, a first inverter, and a second inverter. The first AND gate output is coupled to the first NOR gate first input. The first NOR gate output is coupled to the second NOR gate first input. The second NOR gate output is coupled to the first NOR gate second input. The first inverter output is coupled to the first AND gate second input and the second NOR gate second input. The second AND gate first input is coupled to the first inverter output. The third NOR gate first input is coupled to the second NOR gate output. The third NOR gate second input is coupled to the second AND gate output. The second inverter output is coupled to the second AND gate second input.

An electronic latch circuit (100) and a multi-phase signal generator (300) are disclosed. The electronic latch circuit (100) comprises an output circuit (105) comprising a first output (X, 106), a second output (Y, 107) and a third output (Z, 108). The electronic latch circuit (100) further comprises an input circuit (101) comprising a first input (A, 102), a second input (B, 103) and a clock signal input (CLK, 104). The electronic latch circuit (100) is configured to change state based on input signals at the inputs (A, B, CLK) of the input circuit (101) and a present state of the output circuit (105). The multi-phase signal generator (300) comprises a plurality N of the electronic latch circuit (100) for generating N phase signals with individual phases. The plurality N of the electronic latch circuit (100) are cascaded with each other.

A flip-flop circuit may include a first latch and a second latch. The first latch, which may operate as a “master” latch, includes a first input terminal to receive a data signal, a second input terminal to receive a clock signal, and an output terminal. The second latch, which may operate as a “slave” latch, includes a first input terminal connected directly to the output terminal of the first latch, a second input terminal to receive the clock signal, and an output terminal to provide an output signal. The first latch and the second latch are to be clocked on the same phase of the clock signal, thereby eliminating the need to include clock inversion circuits that generate complementary clock signals.

A semiconductor device includes a first active region, a second active region, a first gate line disposed to overlap the first and second active regions, a second gate line disposed to overlap the first and second active regions, a first metal line electrically connecting the first and second gate lines and providing a first signal to both the first and second gate lines, a first contact structure electrically connected to part of the first active region between the first and second gate lines, a second contact structure electrically connected to part of the second active region between the first and second gate lines, and a second metal line electrically connected to the first and second contact structures and transmitting a second signal, wherein an overlapped region that is overlapped by the second metal line does not include a break region.

A flip flop circuit includes a first master portion, a second master portion, at least one determining portion and a slave portion. The first master portion is configured to operate at a first mode and to receive a first input and generate first master outputs. The second master portion is configured to operate at a second mode and to receive a second input and generate second master outputs. The at least one determining portion is configured to receive at least one enable signal, and has determining inputs and determining outputs. The determining inputs are connected to the first master outputs and the second master outputs. The determining portion is configured to determine the determining outputs being the first master outputs or the second master outputs according to the at least one enable signal. The slave portion is configured to receive the determining outputs and generate an output signal.

A multi-bit flip-flop (MBFF) includes a plurality of 1-bit flip-flops, each having an input data selection circuit that receives a data signal and a scan data signal. The MBFF also includes a local signal generation circuit that receives a global clock signal and a global scan enable signal, and in response, provides local control signals, wherein each of the local control signals is generated in response to both the global clock signal and the global scan enable signal. The local control signals are provided to the input data selection circuits, and exclusively control the input data selection circuits to route either the input data signal or the scan input data signal as a master data bit, reducing transistor requirements. Local clock signals may be generated by the local signal generation circuit in response to the global clock signal, and may exclusively control data transfer within the flip-flops, improving setup time.