An integrated circuit (IC) device includes a master latch circuit having a first clock input and a data output, a slave latch circuit having a second clock input and a data input electrically coupled to the data output of the master latch circuit, and a clock circuit. The clock circuit is electrically coupled to the first clock input by a first electrical connection configured to have a first time delay between the clock circuit and the first clock input. The clock circuit is electrically coupled to the second clock input by a second electrical connection configured to have a second time delay between the clock circuit and the second clock input. The first time delay is longer than the second time delay.

To provide a miniaturized data holding circuit. First and second MOS transistors respectively transmit a data signal and an inverted data signal to inputs of first and second inverting gates that constitute a state holding circuit when a clock signal is at a first level. Fifth and sixth MOS transistors are respectively inserted in a feedback path from an output of the second inverting gate to the input of the first inverting gate and a feedback path from an output of the first inverting gate to the input of the second inverting gate, and respectively transmit the outputs of the second and first inverting gates when the clock signal is at a second signal level. Seventh and eighth MOS transistors are constituted in a channel of a conductive type different from the first MOS transistor and connected in parallel to the fifth and sixth MOS transistors, respectively, and transmit the output of the second inverting gate and the output of the first inverting gate on the basis of the inverted data signal and the data signal, respectively.

A flip-flop circuit includes a clock generator configured to generate first and second clock signals having different phases relative to each other, and a master-slave latch circuit including master and slave latches. The master latch includes a scan path configured to output a scan path signal in response to a scan enable signal and a scan input signal, and a data path configured to output a first latch signal in response to a data signal and the scan path signal. A feedback path is provided, which includes a tri-state inverter responsive to the first and second clock signals. The tri-state inverter has an input terminal connected to an output terminal of the data path and an output terminal connected to a node of the scan path.

A flip-flop circuit includes a first inverter configured to receive a first clock signal and output a second clock signal, a second inverter configured to receive the second clock signal and output a third clock signal, a master stage, and a slave stage including a first feedback inverter and a first transmission gate. The first feedback inverter includes a first transistor configured to receive the first clock signal and a second transistor configured to receive the second clock signal, and the first transmission gate includes first and second input terminals configured to receive the second and third clock signals.

A scan chain architecture with lowered power consumption comprises a multiplexer selecting between a functional input and a test input. The output of the multiplexer is coupled to a low threshold voltage latch and, in test mode, to a standard threshold voltage latch. The low threshold voltage latch and standard threshold voltage latch are configured to store data when a clock input falls, using a master latch functional clock M_F_CLK, master latch test clock M_T_CLK, slave latch functional clock S_F_CLK, and slave latch test clock S_T_CLK. The slave latch has lower power consumption than the master latch.

A flip flop circuit includes a first master portion, a second master portion, at least one determining portion and a slave portion. The first master portion is configured to operate at a first mode and to receive a first input and generate first master outputs. The second master portion is configured to operate at a second mode and to receive a second input and generate second master outputs. The at least one determining portion is configured to receive at least one enable signal, and has determining inputs and determining outputs. The determining inputs are connected to the first master outputs and the second master outputs. The determining portion is configured to determine the determining outputs being the first master outputs or the second master outputs according to the at least one enable signal. The slave portion is configured to receive the determining outputs and generate an output signal.

As a scanning line drive circuit of a display device, a shift register having a configuration in which a plurality of unit circuits are connected to each other in multiple stages is used. The unit circuits each include: a plurality of control transistors; an internal node connected to a terminal of one of the plurality of control transistors; and a depression mode initialization transistor having a first conduction terminal connected directly or through a resistor to the internal node, a second conduction terminal, and a control terminal. One of a power supply voltage and a ground voltage is applied to the second conduction terminal, and the other voltage is applied to the control terminal. The initialization transistor is turned on in a power-off state.

A master latch includes a latch input node and a latch output node, a first inverter with an input and an output, the input coupled to the latch input node and the output coupled to the latch output node, and a second inverter with an input and an output, the input coupled to the latch output node and the output coupled to the latch input node. The master latch further includes a first pull-up device connected between a source voltage and the latch input node, the first pull-up device configured to pull the latch input node up towards the source voltage when the latch output node is low, and a first pull-down device connected between the latch input node and a ground voltage, the first pull-down device configured to pull the latch input node towards the ground voltage when the latch output node is high.

A time to digital converter includes a polarity detecting module and a time digital conversion module. The time digital conversion module includes a digital coding unit, a ring vibration enabling unit, multistage differential time delay units sequentially forming a closed loop in series and a plurality of trigger units. Each differential time delay unit includes a first input end, a second input end, a first output end and a second output end. The first output end and the second output end of each differential time delay unit outputs differential signals which are complementary to each other. Mismatching between the ascending and descending time of a phase inverter and sampling of a trigger can be improved to enable signals entering the trigger units to be phase-complementary signals, thus improving the linearity of digital conversion.

To provide a miniaturized data holding circuit. First and second MOS transistors respectively transmit a data signal and an inverted data signal to inputs of first and second inverting gates that constitute a state holding circuit when a clock signal is at a first level. Fifth and sixth MOS transistors are respectively inserted in a feedback path from an output of the second inverting gate to the input of the first inverting gate and a feedback path from an output of the first inverting gate to the input of the second inverting gate, and respectively transmit the outputs of the second and first inverting gates when the clock signal is at a second signal level. Seventh and eighth MOS transistors are constituted in a channel of a conductive type different from the first MOS transistor and connected in parallel to the fifth and sixth MOS transistors, respectively, and transmit the output of the second inverting gate and the output of the first inverting gate on the basis of the inverted data signal and the data signal, respectively.