The disclosure discloses an RC oscillating circuit. A first end of a capacitor is grounded, a second end of the capacitor is connected to a charging path, a discharging path and a comparator, A first input end of a comparator is connected to first reference voltage. An output end of the comparator outputs a first output signal and is connected to a control end of the discharging path. The first reference voltage provides the flipped voltage of the comparator The first output signal forms an output clock signal. A first regulating circuit is configured to regulate the magnitude of the charging current and realize coarse frequency tuning. A second regulating circuit is configured to regulate the magnitude of the first reference voltage and realize fine frequency tuning. The disclosure has the advantages of low power consumption, fast start, high precision and wide tuning range.

A relaxation oscillator with an aging effect reduction technique comprises a comparator (CP) coupled with its input side (CP1, CP2) to a network comprising at least one capacitor (C, C1, C2), a plurality of transistors (M1, M2, M3, M4) and a plurality of controllable switches (SW11, . . . , SW8, SW111, . . . , SW180). The relaxation oscillator uses a switching method such that the roles of current/voltage generator's transistor and current mirror transistor are periodically swapping by the output signal of the relaxation oscillator. Reducing mismatch of operating points between current/voltage generator and current minor transistors achieves a decrease of frequency degradation caused by aging effect.

A relaxation oscillator with an aging effect reduction technique comprises a comparator (CP) coupled with its input side (CP1, CP2) to a network comprising at least one capacitor (C, C1, C2), a plurality of transistors (M1, M2, M3, M4) and a plurality of controllable switches (SW11, . . . , SW8, SW111, . . . , SW180). The relaxation oscillator uses a switching method such that the roles of current/voltage generator's transistor and current mirror transistor are periodically swapping by the output signal of the relaxation oscillator. Reducing mismatch of operating points between current/voltage generator and current minor transistors achieves a decrease of frequency degradation caused by aging effect.

A current-controlled oscillator receives an input current. Ramp voltage generating circuitry generates first and second ramp voltages in response to the input current. Selecting circuitry selects one of the first and second ramp voltages depending on their relative values. Switching circuitry receives a selected ramp voltage, generates a signal based on the selected ramp voltage relative to a reference voltage, and outputs a clock signal. In one embodiment, a comparator receives the reference voltage, one of the first and second ramp voltages, and outputs a comparison signal. Logic circuitry controls the ramp voltage generating circuitry to output one of the ramp voltages during one half of a clock cycle and to output the other ramp voltage during another half cycle of the clock signal based on the comparison signal and logic states of the logic circuitry.

An electronic circuit is configured to output an output signal after elapse of a predetermined time from a received trigger signal, and includes an oscillator configured to output a pulse signal having a predetermined oscillation frequency; a counter circuit configured to count the pulse signal from the oscillator upon receiving the trigger signal and to output the output signal in response to a count value reaching a predetermined value; and a trimming circuit including a plurality of trimming elements which includes a cuttable conductive part and configured to output a selection signal corresponding to a trimming element having a cut conductive part. In the trimming circuit, the trimming element, which corresponds to the oscillation frequency of the pulse signal output from the oscillator among the plurality of trimming elements, is cut, and the counter circuit is configured to set the predetermined value according to the selection signal.

Integrated circuits having self-calibrating oscillators, and methods of operating the same are disclosed. A disclosed example integrated circuit includes a clock generator, a comparator having a first input connected to an output of the clock generator and a second input connected to a reference voltage, a calibration done detector having an input connected to an output of the comparator and an output communicatively coupled to a calibration code register.

A circuit generates a clock signal with a tunable clock period. The circuit comprises capacitors, first tuning circuitry and second tuning circuitry. The first tuning circuitry is configured to adjust the clock period with a first period tuning step based on a first parameter and the second tuning circuit is configured to adjust the clock period with a second period tuning step based on a second parameter. The first period tuning step is different than the second period tuning step.

A current-controlled oscillator receives an input current. Ramp voltage generating circuitry generates first and second ramp voltages in response to the input current. Selecting circuitry selects one of the first and second ramp voltages depending on their relative values. Switching circuitry receives a selected ramp voltage, generates a signal based on the selected ramp voltage relative to a reference voltage, and outputs a clock signal. In one embodiment, a comparator receives the reference voltage, one of the first and second ramp voltages, and outputs a comparison signal. Logic circuitry controls the ramp voltage generating circuitry to output one of the ramp voltages during one half of a clock cycle and to output the other ramp voltage during another half cycle of the clock signal based on the comparison signal and logic states of the logic circuitry.

Provided is a variable resistance circuit in which the resistance value of the variable resistance circuit can be accurately adjusted, by reducing the error in the change amount of the resistance value of the variable resistance circuit due to the on-resistances of switch circuits even if the switch circuits that each bypass a resistor included in a ladder resistor circuit are switched between an OFF state and an ON state. This variable resistance circuit includes: a ladder resistor circuit including a plurality of resistors; a first switch circuit connected in series to one end of one resistor of the plurality of resistors; and a second switch circuit connected in parallel to a series circuit of the one resistor and the first switch circuit. When one of the first and second switch circuits is turned on, the other of the first and second switch circuits is turned off.

Provided is a variable resistance circuit in which the resistance value of the variable resistance circuit can be accurately adjusted, by reducing the error in the change amount of the resistance value of the variable resistance circuit due to the on-resistances of switch circuits even if the switch circuits that each bypass a resistor included in a ladder resistor circuit are switched between an OFF state and an ON state. This variable resistance circuit includes: a ladder resistor circuit including a plurality of resistors; a first switch circuit connected in series to one end of one resistor of the plurality of resistors; and a second switch circuit connected in parallel to a series circuit of the one resistor and the first switch circuit. When one of the first and second switch circuits is turned on, the other of the first and second switch circuits is turned off.