A power-switch-system (PSS) having a low-side transistor (LSS) and a high-side transistor (HSS), which are switchable to be conductive or switched to be blocking in respectively alternating time-segments of a switching-period of the PSS. A source-terminal of the LSS is connected to a load-terminal, and a drain-terminal of the LSS is connected to a supply-voltage via a storage-inductor. A drain-terminal of the HSS is connected to the load-terminal, and a source-terminal of the HSS is connected to the supply-voltage via the storage-inductor. Provided is a PSS of this kind, the LSS having at least two transistor-segments. At least two of the transistor-segments have a different electrical resistance in the connection to the storage-inductor. The PSS provides that at least two of the transistor-segments are switched at a different point in time during a switching operation of the PSS to reduce unwanted voltage fluctuations, without markedly increasing switching losses.

A switching circuit and a method for providing a switch array having an on resistance is presented. The switch array has a plurality of switches, where each switch is arranged to be in different configuration states. The states include an enabled configuration and a disabled configuration. The switching states include an on state and an off state. Each switch is held in the off state when in the disabled configuration. Control circuitry sets the switches to either the enabled configuration or the disabled configuration, and a memory element coupled to the control circuitry and arranged to store configuration data for setting the configuration state of each of the switches. The control circuitry sets the configuration state of the switches based on a signal received from the memory element. The on resistance of the switch array depends on the switching state of the switches and their individual on resistances.

Disclosed herein are switching or other active FET configurations that implement a main-auxiliary branch design. Such designs include a circuit assembly for performing a switching function that includes a branch including a main path in parallel with a first auxiliary path and the main path in series with a second auxiliary path. The circuit assembly also includes a first gate bias network connected to the main path. The circuit assembly also includes a second gate bias network connected to the first auxiliary path. The circuit assembly also includes a third gate bias network connected to the second auxiliary path, the second gate bias network and the third gate bias network configured to improve linearity of the switching function.

Disclosed herein are switching or other active FET configurations that implement a segmented main-auxiliary branch design. Such designs include a circuit assembly for performing a switching function that includes a branch including a plurality of main-auxiliary pairs coupled in series, wherein each main-auxiliary pair includes a main field-effect transistor (FET) in parallel with an auxiliary FET. The circuit assembly also includes a gate bias network connected to the main FETs and configured to bias the main FETs in a strong inversion region. The circuit assembly also includes an auxiliary bias network connected to the auxiliary FETs and configured to bias the auxiliary FETs in a weak inversion region.

A noise reduction unit includes a plurality of resistors arranged in parallel in a line connected to a device that is charged and discharged and having different resistance values. The noise reduction unit further includes a resistor switch that switches a resistor connected to the device between the plurality of resistors. When the device is discharged, the resistor switch first connects a first one of the plurality of resistors to the device and then connects a second one of the plurality of resistors to the device. The first resistor has a larger resistance value than the second resistor.

An electronic circuit includes a first input pin configured to receive a first input signal that includes an enable information and at least one operation parameter information, a second input pin configured to receive a second input signal, an output pin, a control circuit configured to generate a drive signal based on the first input signal and the second input signal, an output circuit configured to generate an output signal at the output pin, the enable information includes an enabled state and a disabled state, the control circuit is configured to generate the drive signal in the enabled state and to turn to the electronic circuit off in the disabled state, the at least one operation parameter information includes information about an operational parameter of the output signal, and the output circuit is configured to use the at least one operation parameter information to change the operational parameter of the output signal.

Provided are a semiconductor device and a method of operating the same. A semiconductor device may include a comparator which compares a first voltage with a rectified voltage and provides a second voltage in accordance with the comparison. A timer circuit may operate a timer according to the second voltage and output a third voltage in correspondence with an operation time of the timer. A driver may drive a transistor with a fourth voltage generated by the driver according to the third voltage. A calibration circuit may generate a timer calibration signal based on the second voltage and the fourth voltage. The timer calibration signal may be provided to the timer circuit and used to calibrate the operation time of the timer. More efficient rectification, with reduced occurrence of reverse current, may thereby be realized.

The present disclosure relates to a driver device, which can drive a load in high temperatures. In a driver IC which drives a motor by switch-driving four output transistors, a gate driving circuit is configured to render a slew rate of a gate voltage of each output transistor to be adjustable at multiple steps while the output transistor is switching. Although a predetermined rate is set to be the slew rate of the gate voltage in a normal state, the slew rate is increased at high temperatures.

A switching device includes a first leg having a plurality of transistors connected in series. The switching device also includes a second leg having a transistor, connected in parallel to the first leg. The switching device further includes a controller controlling the plurality of transistors and the transistor. The controller is configured to turn the switching device from a first state to a second state by first turning the transistor from the first state to the second stat and then turning the plurality of transistors from the first state to the second state.

In a control device that drives a semiconductor switch element, a first control switch is connected between a signal line and a source terminal or an emitter terminal of a semiconductor switch element. The signal line supplies a driving signal to a gate terminal or a base terminal of semiconductor switch element. The first control switch is controlled to an ON state when the semiconductor switch element is controlled to an OFF state. A second control switch is connected between the signal line and the source terminal or the emitter terminal in parallel with the first control switch. The second control switch is turned on when a potential of the source terminal or the emitter terminal becomes a negative potential.