In a control device that drives a semiconductor switch element, a first control switch is connected between a signal line and a source terminal or an emitter terminal of a semiconductor switch element. The signal line supplies a driving signal to a gate terminal or a base terminal of semiconductor switch element. The first control switch is controlled to an ON state when the semiconductor switch element is controlled to an OFF state. A second control switch is connected between the signal line and the source terminal or the emitter terminal in parallel with the first control switch. The second control switch is turned on when a potential of the source terminal or the emitter terminal becomes a negative potential.

Various examples are provided related to semiconductor topologies and devices that can be used for soft starting and active fault protection of power converters. In one example, an active switch device includes an active switch having a gating control input; and a thyristor having a gating control input. The thyristor is coupled in parallel with the active switch. The active switch can be an IGBT, MOSFET, or other appropriate device. In another example, a power converter can include the active switch devices and switching control circuitry coupled to gating control inputs of the active switch devices.

Some embodiments of the invention include a pre-pulse switching system. The pre-pulsing switching system may include: a power source configured to provide a voltage greater than 100 V; a pre-pulse switch coupled with the power source and configured to provide a pre-pulse having a pulse width of T.sub.pp; and a main switch coupled with the power source and configured to provide a main pulse such that an output pulse comprises a single pulse with negligible ringing. The pre-pulse may be provided to a load by closing the pre-pulse switch while the main switch is open. The main pulse may be provided to the load by closing the main switch after a delay T.sub.delay after the pre-pulse switch has been opened.

In one embodiment, a DC/DC converter includes: a first switching element, a diode connected to the first switching element, an inductor connected to at least one of the first switching element and the diode, and a circuit connected in parallel to the first switching element, the circuit including a second switching element. A current flowing through the circuit when the second switching element is on is smaller than the current flowing through the first switching element when the first switching element is on, and the second switching element is turned on a lead time before the timing at which the first switching element is turned on.

Disclosed herein are switching or other active FET configurations that implement a branch design with one or more interior FETs of a main path coupled in parallel with one or more auxiliary FETs of an auxiliary path. Such designs include a circuit assembly for performing a switching function that includes a branch with a plurality of main FETs coupled in series and an auxiliary FET coupled in parallel with an interior FET of the plurality of main FETs. The body nodes of the FETs can be interconnected and/or connected to a body bias network. The body nodes of the FETs can be connected to body bias networks to enable individual body bias voltages to be used for individual or groups of FETs.

Methods and systems of reducing a substrate noise in a charge pump having a flying capacitor are provided. An input node of the flying capacitor is pre-charged at a first slew rate. The input node of the flying capacitor is charged at a second slew rate that is faster than the first slew rate. The input node of the flying capacitor is pre-discharged at a third slew rate. The input node of the flying capacitor is discharged at a fourth slew rate that is faster than the first slew rate.

A switching device includes a first leg having a plurality of transistors connected in series. The switching device also includes a second leg having a transistor, connected in parallel to the first leg. The switching device further includes a controller controlling the plurality of transistors and the transistor. The controller is configured to turn the switching device from a first state to a second state by first turning the transistor from the first state to the second state and then turning the plurality of transistors from the first state to the second state.

A switching circuit and a method for providing a switch array having an on resistance is presented. The switch array has a plurality of switches, where each switch is arranged to be in different configuration states. The states include an enabled configuration and a disabled configuration. The switching states include an on state and an off state. Each switch is held in the off state when in the disabled configuration. Control circuitry sets the switches to either the enabled configuration or the disabled configuration, and a memory element coupled to the control circuitry and arranged to store configuration data for setting the configuration state of each of the switches. The control circuitry sets the configuration state of the switches based on a signal received from the memory element. The on resistance of the switch array depends on the switching state of the switches and their individual on resistances.

An output circuit including an output transistor configured to provide an output signal; and a gate switch configured to decouple a gate of the output transistor from other components of the output circuit when there is a decrease in a supply voltage of the output circuit, wherein when the gate of the output transistor is decoupled, a charge at the gate is maintained in a capacitor inherent within the gate of the output transistor.

Provided are a semiconductor device and a method of operating the same. A semiconductor device may include a comparator which compares a first voltage with a rectified voltage and provides a second voltage in accordance with the comparison. A timer circuit may operate a timer according to the second voltage and output a third voltage in correspondence with an operation time of the timer. A driver may drive a transistor with a fourth voltage generated by the driver according to the third voltage. A calibration circuit may generate a timer calibration signal based on the second voltage and the fourth voltage. The timer calibration signal may be provided to the timer circuit and used to calibrate the operation time of the timer. More efficient rectification, with reduced occurrence of reverse current, may thereby be realized.