Disclosed herein are switching or other active FET configurations that implement a branch design with one or more interior FETs of a main path coupled in parallel with one or more auxiliary FETs of an auxiliary path. Such designs include a circuit assembly for performing a switching function that includes a branch with a plurality of main FETs coupled in series and an auxiliary FET coupled in parallel with an interior FET of the plurality of main FETs. The body nodes of the FETs can be interconnected and/or connected to a body bias network. The body nodes of the FETs can be connected to body bias networks to enable individual body bias voltages to be used for individual or groups of FETs.

A switching element driving device includes a main on switch that is connected to gates of a first and second IGBTs and that, when brought into a conductive state, turns on the first and second IGBTs, diodes each disposed between the main on switch and one of the gates of the first and second IGBTs, the diodes having a forward direction from the main on switch to the gates of the first and second IGBTs, an on sub-switch that is connected to the gate of the second IGBT and that, when brought into the conductive state, turns on the second IGBT, and a control circuit that controls the conductive state and a non-conductive state of the main on switch and the on sub-switch.

A filter circuit includes a first switch circuit that exclusively connects a first common terminal to either of a first selection terminal and a second selection terminal; a first signal terminal that is connected to the first selection terminal and that is for communicating a first communication signal belonging to a first frequency range, which is a frequency range of a first communication band; a second signal terminal that is connected to the second selection terminal and that is for communicating a second communication signal belonging to a second frequency range, which is the frequency range of a second communication band and which is at least partially overlapped with the first frequency range; and a first band pass filter one end of which is connected to the first common terminal and which uses both the first frequency range and the second frequency range as pass bands.

Techniques are provided for avoiding an avalanche breakdown voltage across a synchronous rectification (SR) switch on the secondary side of an isolated switched-mode power converter operating in a low-power mode, e.g., a burst mode, during which a load of the power converter draws negligible current. This is accomplished via use of a two-level switch driver for controlling a power switch on the primary side of the power converter. The two-level switch driver is configured to source low current levels to a control terminal (e.g., gate) of the power switch during burst-mode operation. This low current reduces the slope of the rising edge of voltage pulses on the primary and secondary sides of the power converter which, in turn, limits the peak of the voltage ringing across the SR switch. By limiting the voltage in this manner, the SR switch avoids entering avalanche breakdown.

A transistor switch circuit includes a first transistor and a set of serially connected transistors. By the configuration of the set of serially connected transistors, the conduction paths of the body diodes of the first transistor can be cut and the body effect thereof is eliminated. Hence, the output signal is prevented from leaking via the conduction path while the first transistor is turned off.

A field effect transistor semiconductor device having a compact device footprint for use in automotive and hot swap applications. The device includes a plurality of field effect transistor cells with the plurality of transistor cells having at least one low threshold voltage transistor cell and at least one high threshold voltage transistor cell arranged on a substrate. The field effect transistor semiconductor device is configured and arranged to operate the at least one high threshold voltage transistor cell during linear mode operation, and operate both the low threshold voltage transistor cell and the high threshold voltage transistor cell during resistive mode operation. Further provided is a method of operating field effect transistor semiconductor device including a plurality of field effect transistor cells that includes at least one low threshold voltage transistor cell and at least one high threshold voltage transistor cell.

Power switch cells (20) respectively includes power switches (21), each of which is capable of performing switching between electrical connection and disconnection between a global power supply line (11) and a local power supply line (8) in accordance with a control signal (CTR). The power switches (21) are connected in a chain state to constitute a chain connection through which the control signal (CTR) is sequentially transmitted. A starting point switch (21a) in the chain connection has a greater distance to an edge (BE) of a region occupied by a power domain than an ending point switch (21b).

Disclosed herein are switching or other active field-effect transistor (FET) configurations that implement independently controlled main-auxiliary branch designs. Such designs include a circuit assembly for performing a switching function that includes a branch with a plurality of main FET devices in parallel with a plurality of auxiliary FET devices. The circuit assembly can include a plurality of gate bias networks where each controls one or more of the main FET devices. The circuit assembly includes a second plurality of gate bias networks that each controls one or more of the auxiliary FET devices.

In a semiconductor integrated circuit employing power gating, a control input signal is propagated to one or more first power switches through a first propagation path and to one or more second power switches through a second propagation path. A restoration determination circuit receives a first signal of the first propagation path and a second signal of the second propagation path and generates a control output signal. When the control signal performs restoration transition, the restoration determination circuit causes the control output signal to perform the restoration transition in accordance with a later timing of timings of restoration transitions of the first and second signals.

Techniques are provided for avoiding an avalanche breakdown voltage across a synchronous rectification (SR) switch on the secondary side of an isolated switched-mode power converter operating in a low-power mode, e.g., a burst mode, during which a load of the power converter draws negligible current. This is accomplished via use of a two-level switch driver for controlling a power switch on the primary side of the power converter. The two-level switch driver is configured to source low current levels to a control terminal (e.g., gate) of the power switch during burst-mode operation. This low current reduces the slope of the rising edge of voltage pulses on the primary and secondary sides of the power converter which, in turn, limits the peak of the voltage ringing across the SR switch. By limiting the voltage in this manner, the SR switch avoids entering avalanche breakdown.