An output buffer circuit includes an output node, a P-type transistor, an N-type transistor, and a first variable resistor circuit provided in a signal path between a drain of one of the P-type transistor and the N-type transistor and the output node.

An electronic device including an electronic switch M1, an electrical pre-charge circuit and a measurement, command and diagnosis module. The main electronic switch M1 has a first electrical terminal D1, a second electrical terminal S1, and a main driving terminal G1. The main electronic switch M1 is adapted to take, based on a driving signal DRV, depending on the command signal CMD and on an enabling signal ENB, a closed condition or an open condition, wherein the first electrical terminal D1 is respectively connected to or disconnected from the second electrical terminal S1. The pre-charge electrical circuit is adapted to carry out, based on the command signal CMD, a pre-charge operation, aimed at equalizing the electric potentials (V1, V2) of the first and second terminals of the device, before the main electronic switch M1 takes a closed condition, upon of a transition from the open condition.

The invention relates to a method (200) and a control device (I) for controlling at least two power semiconductor switches (LHS1 . . . LHSn) connected in parallel for switching a total current (I_ges). The at least two power semiconductor switches (LHS1 . . . LHSn) connected in parallel each have a gate terminal for controlling the respective power semiconductor switch (LHS1 . . . LHS2). An input terminal (EA) for feeding the total current (I_ges), an output terminal (AA) for discharging the total current (I_ges), and a joint control terminal (S) for receiving a joint control signal (SI) that has the state disconnect or connect are provided. The at least two power semiconductor switches (LHS1 . . . LHSn) connected in parallel are connected to the input terminal (EA) at an input end and to the output terminal (AA) at the output end.

An integrated circuit may be provided with power switching circuitry. The power switching circuitry may include a primary power switch and multiple auxiliary power switches. A power gating control circuit may output control signals for selectively activating the primary power switch and at least one of the auxiliary power switches to charge a gated voltage. One or more voltage detectors may be configured to monitor the gated voltage and to activate the remaining auxiliary power switches in response to detecting that the gated voltage exceeds one or more thresholds. Configured and operated in this way, inrush current surge protection can be achieved while charging up the gated voltage sufficiently fast.

A method of controlling a power field-effect transistor includes controlling a plurality of different phases of a gate-to-source voltage of the power field-effect transistor. Without comparing the gate-to-source voltage of the power field effect transistor to a plurality of reference voltages, the method includes discriminating between the different phases of the gate-to-source voltage based on the plurality of reference voltages. At least one of the plurality of reference voltages is based on a threshold voltage of at least one field-effect transistor.

An output buffer circuit includes an output node, a P-type transistor, an N-type transistor, and a first variable resistor circuit provided in a signal path between a drain of one of the P-type transistor and the N-type transistor and the output node.

An electronic circuit includes: a bus bar connected to a power source having a positive terminal and a negative terminal; and a plurality of object switching elements as driving objects connected to the bus bar, the object switching elements forming a parallel connected circuit. The object switching elements include minimum on-resistance elements having minimum on-resistance compared to other object switching elements in a corresponding current region among mutually different current regions; and connection points between the minimum on-resistance elements and the bus bar are located at different locations to have mutually different inductance of respective conduction paths between the power source to the connection points located at the different locations.

A driving apparatus includes a current output unit, a reference voltage output unit, a comparator, and a drive control unit. The current output unit is switchable to either a first ON resistance or a second ON resistance that is N times (N>1) the first ON resistance. The reference voltage output unit outputs a fist reference voltage during a large current time period, and outputs a second reference voltage that is M times (M>1) the first reference voltage during a small current time period. The drive control unit performs control to perform switching to the first ON resistance during the large current time period, and to perform switching to the second ON resistance during the small current time period.

A novel system is offered for supplying power from an input node to a load coupled to an output node. The system may have multiple switches coupled between the input node and the output node. One or more limiting circuits may be configured for controlling the switches so as to limit outputs of the switches. For example, the limiting circuits may limit current through the respective switches. One or more timers may set a delay period for indicating a fault condition after the limiting is initiated.

The present invention provides a drive device and a power supply system capable of driving a power transistor with low power while reflecting variations in manufacture process and external environments. A trigger detection circuit monitors a voltage between terminals or a current between terminals in a switching period of a power transistor and detects that the voltage between terminals or the current between terminals reaches a predetermined reference value. A current switching circuit selects a register outputting a current value to a variable current driver circuit from a plurality of registers and switches the register to be selected using a detection result of the trigger detection circuit as a trigger in the switching period, thereby making the drive current of the variable current driver circuit shift.