A circuit includes a first power node configured to carry a first voltage having a first voltage level, an output node, a node coupled between the first power node and the output node, and a contending transistor coupled between the node and a second power node configured to carry a second voltage having a second voltage level. The circuit generates a signal at the output node that ranges between the first voltage level and a third voltage level, the contending transistor couples the node with the second power node responsive to the signal, a difference between the first voltage level and the second voltage level has a first magnitude, a difference between the first voltage level and the third voltage level has a second magnitude, and the second magnitude is a multiple of the first magnitude having a value greater than one.

In accordance with an embodiment, a method of driving a switching transistor includes receiving an activation signal for the switching transistor and generating a sequence of random values. Upon receipt of the activation signal, a control node of the switching transistor is driven with a drive strength based on a random value of the sequence of random values.

In some examples, an apparatus includes a transistor having a control terminal, in which the transistor is coupled between a power terminal and a ground terminal. The apparatus also includes a resistor. The apparatus also includes a controller having first and second controller inputs and first and second controller outputs, in which the first controller input is coupled to the power terminal, the second controller input is coupled to the control terminal, the first controller output is coupled to the control terminal, and the resistor is coupled between the control terminal and the second controller output.

A circuit includes a first power node having a first voltage level, and an output node. A driver transistor coupled between the first power and output nodes is turned on and off responsive to first and second input signal edge types, respectively. A driver transistor source is coupled with the first power node. A contending circuit includes a slew rate detection circuit that generates a feedback signal based on an output node signal, and a contending transistor between a driver transistor drain and a second voltage. A contending transistor gate receives a control signal based on the feedback signal. The second voltage has a level less than the first voltage level if the output node signal rises responsive to the first input signal edge type, and greater than the first voltage level if the output node signal falls responsive to the first input signal edge type.

A transistor monolithically integrated in a semiconductor body includes a first sub-transistor and a second sub-transistor that both include a first and second load contacts and a control contact for controlling an electric current through a load path. The first load contact of the first sub-transistor is electrically connected to the first load contact of the second sub-transistor and the second load contact of the first sub-transistor is electrically connected to the second load contact of the second sub-transistor. A control circuit is configured to cause the first sub-transistor to switch from a first state to a second state at a first point of time and to cause the second sub-transistor to switch from the first state to the second state at a second point of time subsequent to the first point of time.

Methods, systems, and apparatus for eliminating gate voltage oscillation without increasing switching power loss in paralleled power semiconductor switches at high current turn-off. The damping circuit includes a switch for driving voltage and multiple resistors and multiple inductors. The damping circuit includes multiple capacitors connected to the multiple inductors. The damping circuit includes multiple power semiconductor switches that are connected to the multiple inductors at gate terminals. The damping circuit includes multiple gate terminal resistors connected in parallel to the multiple power semiconductor switches at the gate terminals and multiple gate terminal switches connected to the multiple gate terminal resistors.

A method of increasing a multiplication ratio of a charge pump, the multiplication ratio defining a relationship between an output voltage of the charge pump and an input voltage of the charge pump, comprising: analyzing a first efficiency of the charge pump when the multiplication ratio is at a first ratio, calculating a second efficiency of the charge pump when the multiplication ratio is a second ratio lesser than the first ratio, and based on the first efficiency and the second efficiency, determining at least one of a target output power and a target output voltage at which to change the multiplication ratio from the second ratio to the first ratio.

A load driving device includes: a first turn-on drive circuit turning on a first power device as one of a plurality of gate-driven power devices; a second turn-on drive circuit turning on a second power device as another one of the plurality of gate-driven power devices different from the first power device; a current detection circuit detecting a current in at least the first power device; and a control circuit controlling the first turn-on drive circuit to turn on the first power device by applying a gate voltage with a first change rate, and subsequently controlling the second turn-on drive circuit to turn on the second power device by applying a gate voltage with a second change rate, which is larger than the first change rate, based on a condition in which the current detection circuit does not detect an overcurrent in the first power device.

A novel system is offered for supplying power from an input node to a load coupled to an output node. The system may have multiple switches coupled between the input node and the output node. One or more limiting circuits may be configured for controlling the switches so as to limit outputs of the switches. For example, the limiting circuits may limit current through the respective switches. One or more timers may set a delay period for indicating a fault condition after the limiting is initiated.

The present disclosure relates to the field of circuit design. The embodiments of the present disclosure provide a soft switch circuit, a circuit board assembly, and a switch power supply. The soft switch circuit includes a power supply, a first switch transistor, a second switch transistor, a third switch transistor, a fourth switch transistor, a capacitor, a main inductor, an auxiliary switch transistor, an auxiliary inductor, and a control unit, wherein the control unit is configured to: if the current of the main inductor is positive, turn on the auxiliary switch transistor before the first switch transistor and the fourth switch transistor are turned on; and if the current of the main inductor is negative, turn on the auxiliary switch transistor before the second switch transistor and the third switch transistor are turned on.