An interpolator includes a first delay circuit, a second delay circuit, and a tunable delay circuit. The first delay circuit delays a first input signal for a fixed delay time, so as generate a first output signal. The second delay circuit delays a second input signal for the fixed delay time, so as to generate a second output signal. The tunable delay circuit delays the first input signal for a tunable delay time, so as to generate an output interpolation signal. The tunable delay time is determined according to the first output signal, the second output signal, and the output interpolation signal.

Aspects of the disclosure relate to devices, wireless communication apparatuses, methods, and circuitry for a RF power sensor. One aspect is an apparatus including a power sensor transistor configured to receive a radio frequency (RF) input signal and to generate an output indicative of a power of the RF input signal. The apparatus further includes a current source configured to generate a bias current. Also, the apparatus includes a current mirror, which is formed by the power sensor transistor and a second transistor, configured to provide the bias current to the power sensor transistor. The apparatus further includes a feedback circuit, which is coupled to the power sensor transistor and the second transistor, configured to control a drain current of the second transistor with respect to the bias current.

A semiconductor device includes a hysteresis block configured to generate an output voltage at corresponding disabling enabling voltage levels and a core-voltage-gated (CVG) device configured to receive a core voltage, an input terminal of the hysteresis block is coupled to a control node. The CVG device is configured to alter a control voltage at the control node so as to cause the output voltage of the hysteresis block to be generated at the disabling voltage level in response to the core voltage being at or below a first trigger level. Additionally, the CVG device is configured to alter the control voltage at the control node so as to cause the output voltage of the hysteresis block to be generated at the enabling voltage level in response to the core voltage being at or above a second trigger level, the second trigger level being above the first trigger level.

A device including an inverter circuit, a hysteresis control circuit, and a high-side input level shifter. The inverter circuit having an output and including at least two series connected PMOS transistors connected, at the output, in series to at least two series connected NMOS transistors. The hysteresis control circuit coupled to the output to provide feedback to the at least two series connected PMOS transistors and to the at least two series connected NMOS transistors. The high-side input level shifter connected to gates of the at least two PMOS transistors and configured to shift a low level of an input signal to a higher level and provide the higher level to one or more of the gates of the at least two PMOS transistors.

A N-path filter includes a plurality of switch-capacitor circuits controlled by a plurality of logical signals, respectively, and joined at a common shunt node, each of said switch-capacitor circuit comprising: a respective switch configured to controllably connect the common shunt node to a respective middle node in accordance with a respective logical signals among said plurality of logical signals; and a respective balanced MOS (metal oxide semiconductor) capacitor connected to the respective middle node, wherein the respective balanced MOS capacitor exhibits a capacitance at the respective middle node with reference to a power supply node and a ground node.

A driver circuit includes a first deglitcher circuit that delays a rising edge or a falling edge of an input signal according to a mode control signal and supplies a first output signal. A second deglitcher circuit receives the first output signal and delays either a rising edge or a falling edge of the first output signal by a second delay according to the mode control signal and supplies a second output signal. Logic gates combine the first and second output signals to supply gate control signals for output transistors to drive the driver circuit output. A sum of the first delay and the second delay determines the total deglitch time defining a pulse width of pulses that are suppressed by the driver circuit and the second delay determines a non-overlap time. The non-overlap time overlaps in time with the total deglitch time.

A supply voltage detecting circuit has a voltage detection circuit and a current clamping circuit. The voltage detection circuit receives and detects a supply voltage and is used to detect to generate a low-voltage detection signal. When the supply voltage is lower than a set level, the low voltage detection signal output by the voltage detection circuit turns off the current clamping circuit, and a transistor current flowing through the voltage detection circuit is proportional to the supply voltage; and when the supply voltage is higher than or equal to the set level, the low voltage detection signal output by the voltage detection circuit turns on the current clamping circuit, and the current clamping circuit provides a constant current to maintain the operation of the voltage detection circuit, wherein the transistor current flowing through the voltage detection circuit is proportional to the constant current.

An Inter-IC interface with a glitch filter including at least two cascaded RC filters configured to compensate a signal skew of the data or clock signal received from a data communication or clock signal line, feedback switches configured to pull up or pull down a voltage at an output node of each of the at least two cascaded RC filters, and feedforward transistors configured to condition a respective switch to the feedback switches to accelerate the pull up or the pull down.

A multiplexer includes an input, an output, and a main switch configured to pass a signal from the input to the output. The multiplexer includes two bootstrap circuits that collectively maintain a constant voltage between terminals of the main switch during alternating phases.

An output stage of an Ethernet transmitter is provided. The output stage is coupled to a resistor and includes a first output terminal, a second output terminal, a first transistor, and a first transistor group. The resistor is coupled between the first output terminal and the second output terminal. The first transistor has a first source, a first drain, and a first gate, the first source being coupled to a first reference voltage and the first drain being coupled to the second output terminal. The first transistor group is coupled to the first reference voltage and the first output terminal. The first transistor group includes multiple transistors which are connected in parallel, and the magnitude of the current flowing to the first output terminal is related to the number of transistors that are turned on.