The object of the present disclosure is to provide a power semiconductor device capable of miniaturization. According to the present disclosure power semiconductor device includes a semiconductor switching element configured to control a current flowing through a primary coil composing an ignition coil, and a control circuit configured to control drive of the semiconductor switching element, in which the control circuit includes a first constant current source, a first transistor with an output terminal thereof connected to a control terminal of the semiconductor switching element, a resistor with one end thereof connected to a control terminal of the first transistor and an other end thereof connected to the constant current source, a capacitor with one end thereof connected to the control terminal of the first transistor and an other end thereof grounded, and a second transistor with an input terminal thereof connected to the resistor and an output terminal grounded.

An analogue switch arrangement includes an analogue switch including a first and second transistor in parallel between an input terminal and an output terminal and an input transistor arrangement including a first control transistor, a second control transistor, a first voltage control transistor and a second voltage control transistor. The gate terminals of both the first and second transistors are configured to receive a first and second control signal for controlling the analogue switch between an on-state and an off-state. The gate terminals of both the first and second voltage control transistors are configured to receive a voltage based on the voltage at the output terminal to provide for control of the voltage applied at the input terminal based on the voltage at the output terminal when the analogue switch is in the off-state.

The circuit device includes a first MOS transistor of a first conductivity type a source of which is coupled to a first power supply voltage node, a second MOS transistor of a second conductivity type a source of which is coupled to a second power supply voltage node, a first variable resistance circuit which is coupled between a drain of the first MOS transistor and an output node, and which includes a first switch, and a second switch coupled between the drain of the first MOS transistor and the second power supply voltage node. The control circuit performs control of making the first switch OFF and making the second switch ON when the clock signal fails to be output from the output node, and making the first switch ON and making the second switch OFF when the clock signal is output from the output node.

Disclosed are a full-wave drive circuit for an ultrasonic atomizing sheet and an ultrasonic electronic cigarette. In an embodiment, the ultrasonic atomizing sheet full-wave drive circuit comprises a power supply module, a microprocessor, a high-frequency square wave generation circuit, an NMOS transistor and a resonance circuit configured to convert, on the basis of the NMOS transistor, a voltage signal outputted by the high-frequency square wave generation circuit into a full-wave oscillation signal, so as to drive the ultrasonic atomizing sheet to perform full-wave oscillation. A disclosed embodiment has low requirements for a boost module, low loss of the boost module, high power conversion efficiency, small volume, low loss of NMOS transistor and low cost, is easy for debugging, and has high reliability and good atomization effect.

A sampling switch circuit, including an input node, which receives an input voltage signal to be sampled, a sampling transistor having gate, source and drain terminals, the source terminal connected to the input node, a capacitor, a current source configured to cause a defined current to flow therethrough and switching circuitry configured to alternate between a precharge configuration and an output configuration depending upon a clock signal. In the precharge configuration, the switching circuitry connects the capacitor into a current path between said current source and a first voltage reference node to form a potential difference across the capacitor which is dependent on the defined current. In the output configuration, the switching circuitry connects the capacitor between a second voltage reference node and the gate terminal of the sampling transistor so that a voltage level applied at the gate terminal of the sampling transistor is dependent on the defined current.

An output circuit includes: a first input transistor that is provided between a first power supply line and a first intermediate node; a second input transistor that is provided between a second intermediate node and a second power supply line; a first cascode transistor that is provided between the first intermediate node and an output node, and receives a first clip voltage from a first voltage generation circuit; a second cascode transistor that is provided between the output node and the second intermediate node, and receives a second clip voltage from a second voltage generation circuit; a first switch transistor that is provided between the first intermediate node and a gate of the first cascode transistor, and turns on during power down; and a second switch transistor that is provided between the second intermediate node and a gate of the second cascode transistor, and turns on during power down.

Methods and devices used to cancel non-linear capacitances in high power radio frequency (RF) switches manufactured in bulk complementary metal-oxide-semiconductor (CMOS) processes are disclosed. The methods and devices are also applicable to stacked switches and RF switches fabricated in silicon-on-insulator (SOI) technology.

An integrated circuit includes a clocking transistor, a first enabling transistor, a second enabling transistor, a branch-one transistor, a branch-two transistor, and a clock gating circuit. The first enabling transistor is coupled between the clocking transistor and a first node. The second enabling transistor is coupled between the clocking transistor and a second node. The branch-one transistor is coupled between a first power supply and the first node. The gate terminal of the branch-one transistor is electrically connected to the second node. The branch-two transistor is coupled between the first power supply and the second node. The gate terminal of the branch-two transistor is electrically connected to the first node. The clock gating circuit for generating a gated clock signal receives a latch output signal which is latched to a logic level of either a first node signal or a second node signal.

An electronic device includes an internal voltage driving circuit configured to drive an internal voltage to one of first and second power supply voltages based on a driving control signal depending on an operating frequency. The electronic device includes a driving control signal generation circuit configured to generate the driving control signal that sets a level of the internal voltage, by detecting the level of the internal voltage.

Embodiments of a differential bootstrapped track-and-hold circuit are disclosed. In an embodiment, the differential bootstrapped track-and-hold circuit includes first and second single-ended bootstrapped track-and-hold circuits. Each single-ended bootstrapped track-and-hold circuit includes a sampling switch connected between an input terminal and an output terminal, a sampling capacitor connected to the output terminal, and a dummy sampling switch connected between the input terminal and a dummy output terminal. The sampling switch and the dummy sampling switch are controlled by a bootstrap driver connected to the input terminal. The dummy output terminal of the first single-ended bootstrapped track-and-hold circuit is connected to the output terminal of the second single-ended bootstrapped track-and-hold circuit and the dummy output terminal of the second single-ended bootstrapped track-and-hold circuit is connected to the output terminal of the first single-ended bootstrapped track-and-hold circuit to provide signals to compensate for charge injection errors at the output terminals.