Disclosed is a circuit for converting a temperature change amount into a voltage change amount in a motor drive system, including a positive temperature change rate voltage generation module, a circuit bias module, and a temperature detection module that are integrated on a same substrate. An external power supply voltage is processed by the positive temperature change rate voltage generation module and the circuit bias module, and then inputted to the temperature detection module. The temperature detection module detects in real time the temperature change amount in the motor drive system, convert the temperature change amount into the voltage change amount, and transfer the voltage change amount to the circuit bias module, to allow the circuit bias module to output the voltage change amount. In this way, the conversion from the temperature change amount into the voltage change amount is realized.

A multiplexer circuit includes first and second fins each extending in an X-axis direction. First, second, third and fourth gates extend in a Y-axis direction perpendicular to the X-axis direction and contact the first and second fins. The first, second, third and fourth gates are configured to receive first, second, third and fourth data signals, respectively. Fifth, sixth, seventh and eighth gates extend in the Y-axis direction and contact the first and second fins, the fifth, sixth, seventh and eighth gates, and are configured to receive the first, second, third and fourth select signals, respectively. An input logic circuit is configured to provide an output at an intermediate node. A ninth gate extends in the Y-axis direction and contacts the first and second fins. An output logic circuit is configured to provide a selected one of the first, second, third and fourth data signals at an output terminal.

A filp-flop circuit includes master latch including a first inverter and a first tri-state inverter, wherein the first tri-state inverter includes a first NMOS transistor and a first PMOS transistor; a slave latch including a second inverter and a second tri-state inverter, wherein the second tri-state inverter includes a second PMOS transistor and a second NMOS transistor; and at least one of a first wiring configured to connect a source of the first PMOS transistor and a source of the first NMOS transistor and a second wiring configured to connect a source of the second PMOS transistor and a source of the second NMOS transistor.

A filp-flop circuit includes master latch including a first inverter and a first tri-state inverter, wherein the first tri-state inverter includes a first NMOS transistor and a first PMOS transistor; a slave latch including a second inverter and a second tri-state inverter, wherein the second tri-state inverter includes a second PMOS transistor and a second NMOS transistor; and at least one of a first wiring configured to connect a source of the first PMOS transistor and a source of the first NMOS transistor and a second wiring configured to connect a source of the second PMOS transistor and a source of the second NMOS transistor.

An integrated circuit includes a first and second active region, a first insulating region, and a first and second contact. The first and second active regions extend in a first direction, are in a substrate, and are located on a first level. The first active region includes a first drain/source region and a second drain/source region. The second active region includes a third drain/source region. The first insulating region is over the first drain/source region. The first contact extends in a second direction, overlaps the third drain/source region, is electrically coupled to the third drain/source region and is located on a second level. The second contact extends in at least the second direction, overlaps the first insulating region and the first contact. The second contact is electrically insulated from the first drain/source region, is electrically coupled to the third drain/source region, and is located on a third level.

An integrated circuit includes a first and second active region, a first insulating region, and a first and second contact. The first and second active regions extend in a first direction, are in a substrate, and are located on a first level. The first active region includes a first drain/source region and a second drain/source region. The second active region includes a third drain/source region. The first insulating region is over the first drain/source region. The first contact extends in a second direction, overlaps the third drain/source region, is electrically coupled to the third drain/source region and is located on a second level. The second contact extends in at least the second direction, overlaps the first insulating region and the first contact. The second contact is electrically insulated from the first drain/source region, is electrically coupled to the third drain/source region, and is located on a third level.

An electronic control device includes a plurality of control circuit units, a signal line, and a sneak-in suppression circuit. The plurality of control circuit units are connected to separate grounds, respectively. The signal line connects a first control circuit unit and a second control circuit unit. When a system is defined as a combination of a component and a ground corresponding to a control circuit unit, the sneak-in suppression circuit suppresses a sneak-in of electric power from the ground of one system (i.e., a subject system) to the other system connected by the signal line for preventing a cascading failure.

An electronic control device includes a plurality of control circuit units, a signal line, and a sneak-in suppression circuit. The plurality of control circuit units are connected to separate grounds, respectively. The signal line connects a first control circuit unit and a second control circuit unit. When a system is defined as a combination of a component and a ground corresponding to a control circuit unit, the sneak-in suppression circuit suppresses a sneak-in of electric power from the ground of one system (i.e., a subject system) to the other system connected by the signal line for preventing a cascading failure.

A level shifter includes a pre-level shifter and a selector. The selector is coupled to the pre-level shifter. The pre-level shifter shifts an input digital voltage to a first digital voltage and a second digital voltage. The levels of the first digital voltage and the second digital voltage transition sequentially in time when the level of the input digital voltage transitions from one logic to the other. The selector selects and outputs the first digital voltage whose level transitions earlier in time compared to the transition of the level of the second digital voltage.

A semiconductor integrated circuit includes a first semiconductor layer, a second semiconductor layer, and a first cell and a second cell which are arranged adjacent to each other along a first direction. Each of the first cell and the second cell has a polygonal boundary shape with n (where, n is a natural number of >4) sides. The first cell includes a plurality of first MOS transistors and a plurality of second MOS transistors. The second cell includes a plurality of third MOS transistors and a plurality of fourth MOS transistors. The first cell and the second cell are arranged such that each of the first cell and the second cell has a region overlapping with each other in a second direction.