A tunable homojunction field effect device-based unit circuit and a multifunctional logic circuit, and the corresponding design scheme includes four steps: a structural construction of the tunable homojunction device, an implementation of multi-functional electrical operations of the tunable homojunction device, a design of a basic logic unit circuit, and an implementation of complex logic functions by a cascaded unit logic circuit; the first designs a tunable homojunction device based on a material with bipolar field effect characteristics; and then introduces the polarity of source-drain voltage into the device as an additional control signal; further, by cascading three reconfigurable logic units, the multi-functional logic circuit that can perform logic functions of full adder and subtractor is designed; the logic unit circuit designed in the present invention has the ability to perform reconfigurable logic functions.

Device and a method of configuring a voltage level shifter is disclosed. The device includes a traditional level shifter circuit (TLSC), a first control circuit (FCC) cross-coupled to a second control circuit (SCC). The FCC is coupled to receive an inverse of an input at a first input node and provide a first output at a first output node. The SCC is coupled to receive the input at a second input node and provide a second output at a second output node and the TLSC is configured to provide an output at an output node in response to the first output received at the first output node and the second output received at the second output node. A first power source is configured to provide a first power supply voltage to the TLSC, the FCC and the SCC. The output is latched to track the input. The TLSC, the FCC and the SCC are coupled to a ground reference node.

Device and a method of configuring a voltage level shifter is disclosed. The device includes a traditional level shifter circuit (TLSC), a first control circuit (FCC) cross-coupled to a second control circuit (SCC). The FCC is coupled to receive an inverse of an input at a first input node and provide a first output at a first output node. The SCC is coupled to receive the input at a second input node and provide a second output at a second output node and the TLSC is configured to provide an output at an output node in response to the first output received at the first output node and the second output received at the second output node. A first power source is configured to provide a first power supply voltage to the TLSC, the FCC and the SCC. The output is latched to track the input. The TLSC, the FCC and the SCC are coupled to a ground reference node.

Methods, apparatus, systems, and articles of manufacture are disclosed to buffer an input voltage. An example apparatus includes first inverter circuitry to invert the input voltage and produce a first inverted voltage; second inverter circuitry coupled to the first inverter circuitry, the second inverter circuitry to invert the first inverted voltage and produce a second inverted voltage at a rate based on a first current controlled transistor; third inverter circuitry coupled to the second inverter circuitry, the third inverter circuitry to invert the second inverted voltage and produce a third inverted voltage at a rate based on a second current controlled transistor; and fourth inverter circuitry coupled to the third inverter circuitry, the fourth inverter circuitry to invert the third inverted voltage and produce an output voltage, wherein the output voltage matches the input voltage.

Methods, apparatus, systems, and articles of manufacture are disclosed to buffer an input voltage. An example apparatus includes first inverter circuitry to invert the input voltage and produce a first inverted voltage; second inverter circuitry coupled to the first inverter circuitry, the second inverter circuitry to invert the first inverted voltage and produce a second inverted voltage at a rate based on a first current controlled transistor; third inverter circuitry coupled to the second inverter circuitry, the third inverter circuitry to invert the second inverted voltage and produce a third inverted voltage at a rate based on a second current controlled transistor; and fourth inverter circuitry coupled to the third inverter circuitry, the fourth inverter circuitry to invert the third inverted voltage and produce an output voltage, wherein the output voltage matches the input voltage.

A semiconductor device, comprising at least one active region; at least one MD region formed over a portion of the at least one active region; and at least one gate electrode formed over a portion of the at least one active region different than the portion of the active region where the MD region is formed. The semiconductor device further comprises at least one metal layer over at least a portion of the at least one active region, the at least one metal layer being located on a layer of the semiconductor device, different than the layers on which the at least one MD region and at least one gate electrode are formed. A via is formed over the at least one active region and configured to connect one of the at least one gate electrodes to one of the at least one metal layers. The at least one metal layer is configured to enable the at least one gate electrode to be connected to another at least one electrode and/or at least one MD region.

A semiconductor device, comprising at least one active region; at least one MD region formed over a portion of the at least one active region; and at least one gate electrode formed over a portion of the at least one active region different than the portion of the active region where the MD region is formed. The semiconductor device further comprises at least one metal layer over at least a portion of the at least one active region, the at least one metal layer being located on a layer of the semiconductor device, different than the layers on which the at least one MD region and at least one gate electrode are formed. A via is formed over the at least one active region and configured to connect one of the at least one gate electrodes to one of the at least one metal layers. The at least one metal layer is configured to enable the at least one gate electrode to be connected to another at least one electrode and/or at least one MD region.

A method for providing a logic synthesis of a pipeline circuit is disclosed. The method includes: providing a circuit design of the pipeline circuit, wherein the circuit design includes a first logic module as a current stage, and based on an operation of the first logic module, generating a first time marked graph (TMG) that corresponds to a plurality of behavioral phases of the first logic module, wherein the first TMG includes a plurality of vertexes and edges, wherein each vertex corresponds to one of the plurality of behavioral phases that occur in sequence and each edge is coupled between two respective vertexes thereby corresponding to a transition from one behavioral phase to another subsequently occurring behavioral phase.

Techniques are described to address P-MOS bias temperature instability (BTI) stress issues within capacitive radio frequency digital-to-analog converter (CDAC) using a circuit architecture solution that functions to protect the transistors in various operating conditions. Techniques are disclosed that function to float one or both of the negative and positive power supply rail voltages higher or lower, respectively, for CDAC cells depending upon various operating scenarios. These scenarios include the transmitting state of individual CDAC cells and the transmitting state of the CDAC array in which the CDAC cell is implemented.

Techniques are described to address P-MOS bias temperature instability (BTI) stress issues within capacitive radio frequency digital-to-analog converter (CDAC) using a circuit architecture solution that functions to protect the transistors in various operating conditions. Techniques are disclosed that function to float one or both of the negative and positive power supply rail voltages higher or lower, respectively, for CDAC cells depending upon various operating scenarios. These scenarios include the transmitting state of individual CDAC cells and the transmitting state of the CDAC array in which the CDAC cell is implemented.