A synchronization circuit includes a precharge circuit and a signal driving circuit. The precharge circuit precharges an output node to a first logic level. The signal driving circuit detects, in synchronization with a second dock signal having a phase leading a first clock signal, a logic level of an input signal and drives, in synchronization with the first clock signal, the output node to a second logic level according to the logic level of the input signal.

Reduced-power dynamic data circuits with wide-band energy recovery are described herein. In one embodiment, a circuit system comprises at least one sub-circuit in which at least one of the sub-circuits includes a capacitive output node that is driven between low and high states in a random manner for a time period and an inductive circuit path coupled to the capacitive output node. The inductive circuit path includes a transistor switch and an inductor connected in series to discharge and recharge the output node to a bias supply. A pulse generator circuit generates a pulse width that corresponds to a timing for driving the output node.

Reduced-power dynamic data circuits with wide-band energy recovery are described herein. In one embodiment, a circuit system comprises at least one sub-circuit in which at least one of the sub-circuits includes a capacitive output node that is driven between low and high states in a random manner for a time period and an inductive circuit path coupled to the capacitive output node. The inductive circuit path includes a transistor switch and an inductor connected in series to discharge and recharge the output node to a bias supply. A pulse generator circuit generates a pulse width that corresponds to a timing for driving the output node.

A clocked latch circuit includes an amplification circuit, a latch circuit, a first current source, and a second current source. The amplification circuit changes voltage levels of first and second output signals based on a clock signal, a first input signal, and a second input signal. The latch circuit maintains the voltage levels of the first and second output signals based on a complementary signal of the clock signal. The first current source allows a first current to flow to activate the amplification circuit. The second current source allows a second current that is different from the first current to flow to activate the latch circuit.

An integrated circuit includes a first circuit, a second circuit, and an inverter. The first circuit receives a first input signal, an inverted clock signal, a first logic level of a first output node, and a logic level of a second output node to determine a second logic level of a first output node. The second circuit receives the first input signal, the clock signal, the first logic level, and the second logic level to determine a logic level of the second output node. The inverter receives a second input signal to output the inverted second input signal to the first circuit or the second circuit. A logic level of the first output node or a logic level of the second output node is output as an output signal when a logic level of the clock signal is a first logic level.

Combined physical unclonable function (PUFs); methods, apparatuses, systems, and computer program products for enrolling combined PUFs; and methods, apparatuses, systems, and computer program products for authenticating a device physically associated with a combined PUF are described. In an example embodiment, a combined PUF includes a plurality of PUFs and one or more logic gates. Each PUF includes a plurality of stages and an arbiter configured to generate a single PUF response based on response portions generated by the plurality of stages. The one or more logic gates are configured to combine the single PUF response for each of the plurality of PUFs in accordance with a combination function to provide a combined response.

Circuits, methods, and systems for generating data outputs based on sampled data inputs. One circuit includes a first latch including a first logic gate, a second logic gate, and a first keeper subcircuit. The circuit further includes a second latch including a third logic gate, a fourth logic gate, and a second keeper subcircuit. The first keeper subcircuit being electrically coupled via a first shared node of the first latch and the second latch, and the second keeper subcircuit being electrically coupled via a second shared node of the first latch and the second latch.

A dynamic logic circuit including a first transistor within a first device stratum of a substrate; and a second transistor within a second device stratum of the substrate that is different from the first device stratum, wherein the first transistor and the second transistor share a common gate electrode. A method including disposing a second semiconductor body of a second transistor on a first semiconductor body of a first transistor in a first device stratum on a substrate, the second semiconductor body defining a second device stratum; and forming a common gate electrode on each of the semiconductor body and the second semiconductor body.

Integrated circuit devices are provided. The devices may include a substrate including a first region, a second region and a boundary region between the first and second regions. The first and second regions may be spaced apart from each other in a first horizontal direction. The devices may also include a first latch on the first region, a second latch on the second region, and a conductive layer extending in the first horizontal direction and crossing over the boundary region. The first latch may include a first vertical field effect transistor (VFET), a second VFET, a third VFET, and a fourth VFET. The second latch may include a fifth VFET, a sixth VFET, a seventh VFET, and an eighth VFET. The first and seventh VFETs may be arranged along the first horizontal direction. Portions of the conductive layer may include gate electrodes of the first and seventh VFETs, respectively.

A PUF generator includes a difference generator circuit with first and second transistors having a first predetermined VT. The difference generator circuit is configured to provide a first output signal for generating a PUF signature based on respective turn on times of the first and second transistors. An amplifier includes a plurality of transistors having a second predetermined VT. The amplifier is configured to receive the first output signal and output the PUF signature.