An electrical circuit includes a driver circuit, a receiver circuit, and a keeper circuit. The receiver circuit receives an input pulse from the driver circuit during a pre-charge phase. The receiver circuit generates an output pulse based on the input pulse during an evaluation phase. The keeper circuit maintains a charge of the output pulse until another evaluation phase, wherein the keeper circuit is adapted to the driver circuit by gating a first voltage supply of the driver circuit with a second voltage supply of the keeper circuit.

Integrated circuit devices are provided. The devices may include a substrate including a first region, a second region and a boundary region between the first and second regions. The first and second regions may be spaced apart from each other in a first horizontal direction. The devices may also include a first latch on the first region, a second latch on the second region, and a conductive layer extending in the first horizontal direction and crossing over the boundary region. The first latch may include a first vertical field effect transistor (VFET), a second VFET, a third VFET, and a fourth VFET. The second latch may include a fifth VFET, a sixth VFET, a seventh VFET, and an eighth VFET. The first and seventh VFETs may be arranged along the first horizontal direction. Portions of the conductive layer may include gate electrodes of the first and seventh VFETs, respectively.

a logic operation circuit, includes at least one differential logic operation circuit, the differential logic operation circuit includes a logic network module, a differential amplifier module, and a differential amplifier module. The logic network module includes a first logic network unit and a second logic network unit with functions complementarity to each other. A differential signal is generated based on input signals of the first logic network unit and the second logic network unit, the first logic network and the second logic network performs a predetermined logic function to output an operation result based on the input signals. The differential amplifier module, includes a first input terminal, a second input terminal, a first output terminal, a second output terminal, the first input terminal and the second input terminal are connected to an output of the first logic network and the second logic network respectively.

A dynamic logic circuit including a first transistor within a first device stratum of a substrate; and a second transistor within a second device stratum of the substrate that is different from the first device stratum, wherein the first transistor and the second transistor share a common gate electrode. A method including disposing a second semiconductor body of a second transistor on a first semiconductor body of a first transistor in a first device stratum on a substrate, the second semiconductor body defining a second device stratum; and forming a common gate electrode on each of the semiconductor body and the second semiconductor body.

A level shifter comprises a first control switch (207) for connecting an output terminal to a first supply voltage (VDDH) to set an output signal to be high, and a second control switch (208) for connecting the output terminal to a signal ground (GND) to set the output signal to be low. The level shifter comprises a pre-charging switch (210) for connecting the output terminal to the first supply voltage, and an input gate circuit (211) for controlling an ability of an input signal to control the second control switch. The level shifter comprises a keeper circuit (212) for controlling the first control switch based on the output signal. The first control switch is controlled with the first supply voltage when the output signal is low, and with a second supply voltage that is between the first supply voltage and the signal ground when the output signal is high.

An embodiment of the present invention relates to a low-power broadband asynchronous BPSK demodulation method and a configuration of a circuit thereof. In connection with a configuration of a BPSK demodulation circuit, there may be provided a low-power wideband asynchronous binary phase shift keying demodulation circuit comprising: a sideband separation and lower sideband signal delay unit; a data demodulation unit; and a data clock restoration unit.

Circuits and methods that use harvested electrostatic energy from transient: on-chip data are described in the Application. In one aspect, a method inverter circuit use harvested electrostatic charge held at any electric potential higher than the common ground reference potential of CMOS circuits in a chip, to partially drive a 0.fwdarw.1 logic transition at the output of the inverter at lower energy drain from the on-chip power grid than a conventional CMOS inverter with similar performance, slew rates at inverter input and output and with similar output driving transistor geometries.

Circuits and methods that harvest electrostatic energy from transient on-chip data are described in the Application. In one aspect, a method and inverter circuit harvests electrostatic charge held at its output node at an electric potential comparable to the power supply voltage rail to a common grid/node as the output makes a 1.fwdarw.0 logic transition. This charge harvested at a common grid/node can be used by circuits (described in applications 63/090,169, 63/139,744) to drive 0.fwdarw.1 logic transition at their output nodes at lower energy drain from the on-chip power grid than a conventional CMOS inverter would with similar performance, slew rates at inverter input and output and with similar output driving transistor geometries.

A plurality of dynamic decode circuits for decoding a plurality of input signals comprises a decoder that decodes the plurality of input signals to produce a result at a first node, the result is propagated to a second node while an evaluation clock is active by a pair of serially connected transistors consisting of a transistor receiving an evaluation clock at its gate and a transistor receiving the first node at its gate, the plurality of dynamic decode circuits sharing a conditioned node.

A method for adiabatic charging of a capacitive load sequentially connects outer switches between a voltage V.sub.DD and ground and inner switches to at least one capacitance that self-balances between V.sub.DD and ground. A voltage waveform is provided to the capacitive load from a common node of the outer switches and the inner switches. An adiabatic charging circuit includes outer transistor switches between a voltage V.sub.DD and ground. Inner transistor switches are connected to at least one capacitance that self-balances between V.sub.DD and ground. A control signal generating circuit generates control signals for the inner and outer transistor switches that sequentially turn the inner and outer switches on and off to create a multi-level voltage staircase waveform at a common node of the inner and outer transistor switches.