An reciprocal quantum logic (RQL) gate circuit has a first stage having four logical inputs asserted based on receiving positive single flux quantum (SFQ) pulses and storing the SFQ pulses in respective storage loops each associated with a logical input, and a second stage having two more storage loops. First and second logical decision Josephson junctions (JJs) make determinations based on signals stored in the first-stage storage loops. A third logical decision JJ makes a third determination based on the first and second determinations. Each logical decision JJ triggers based on biasing provided by one or more currents stored in its associated storage loops and a bias signal having an AC component. The second stage asserts an output based on the triggering of the third logical decision JJ. Four-input AND, OR, AO22, and OA22 gates are thereby provided.

A method includes receiving, at a field programmable gate array (FPGA), one or more Ethernet packets of a message including control or status information associated with the FPGA. The method also includes determining, by the FPGA, a payload of each packet by removing at least one Ethernet header from the packet. The method further includes removing, by the FPGA, a User Datagram Protocol (UDP) header from each packet and determining UDP header metadata. The method also includes converting, by the FPGA based on the UDP header metadata, the packets to a read or write message associated with one or more registers of the FPGA. In addition, the method includes performing, by the FPGA, a read or write of the one or more registers of the FPGA according to the read or write message.

Unique systems, methods, techniques and apparatuses of a gate driver are disclosed herein. One exemplary embodiment is a gate driver comprising a first and second DC rail, a first converter arm including a first and second semiconductor device, a second converter arm including a third and fourth semiconductor device, an inductor, and a controller. The controller is configured to open and close the primary switching device by operating the semiconductor devices so as to transmit power between the gate driver and a gate of a primary switching device. The controller is configured to transmit a gate signal to the primary switching device by closing the second semiconductor device, then opening the second semiconductor device and closing the fourth semiconductor device in response to the gate of the primary switching device receiving power with a voltage greater than or equal in magnitude to the voltage of the second DC rail.

Unique systems, methods, techniques and apparatuses of a gate driver are disclosed herein. One exemplary embodiment is a gate driver comprising a first and second DC rail, a first converter arm including a first and second semiconductor device, a second converter arm including a third and fourth semiconductor device, an inductor, and a controller. The controller is configured to open and close the primary switching device by operating the semiconductor devices so as to transmit power between the gate driver and a gate of a primary switching device. The controller is configured to transmit a gate signal to the primary switching device by closing the second semiconductor device, then opening the second semiconductor device and closing the fourth semiconductor device in response to the gate of the primary switching device receiving power with a voltage greater than or equal in magnitude to the voltage of the second DC rail.

A feedback control system may include a feedback controller for controlling a plant using pulse density signals. The feedback controller may include a pulse density signal generator and a controller logic circuit. The pulse density signal generator may receive input command signals and generate signed or unsigned pulse density input signals. The controller logic may receive the pulse density input signals from the pulse density signal generator and feedback pulse density signals from the plant and may generate corresponding pulse density control signals for controlling the plant based on the input command signals. The controller logic may include a sign change logic, an addition circuit, and an optional amplifier circuit. The pulse density signal generator may also include rate transition circuits for ensuring that the pulse density input signals and the feedback pulse density signals are uncorrelated.

According to an embodiment, a programmable logic circuit is described comprising a first data bit input to receive a first data bit a and a second data bit input to receive a second data bit b, a first program bit input to receive a first program bit p.sub.1, a second program bit input to receive a second program bit p.sub.2, a third program bit input to receive a third program bit p.sub.3 and a fourth program bit to receive a fourth program bit p.sub.4 and an output configured to output

[00001]$\stackrel{\_}{\left(\stackrel{\_}{\left(\left(a.Math.b\right)\left(p_1.Math.a\right)\left(p_2.Math.b\right)\right)}.Math.\left(p_{3}ba\right)\right)\left(a.Math.b.Math.p_4\right)}.$

A novel semiconductor device is provided. The semiconductor device includes a programmable logic device including a programmable logic element, a control circuit, and a detection circuit. The programmable logic device includes a plurality of contexts. The control circuit is configured to control selection of the contexts. The detection circuit is configured to output a signal corresponding to the amount of radiation. The control circuit is configured to switch between a first mode and a second mode in accordance with the signal corresponding to the amount of radiation. The first mode is a mode in which the programmable logic device performs processing by a multi-context method, and the second mode is a mode in which the programmable logic device performs processing using a majority signal of signals output from the logic element multiplexed by the plurality of contexts.

A feedback control system may include a feedback controller for controlling a plant using pulse density signals. The feedback controller may include a pulse density signal generator and a controller logic circuit. The pulse density signal generator may receive input command signals and generate signed or unsigned pulse density input signals. The controller logic may receive the pulse density input signals from the pulse density signal generator and feedback pulse density signals from the plant and may generate corresponding pulse density control signals for controlling the plant based on the input command signals. The controller logic may include a sign change logic, an addition circuit, and an optional amplifier circuit. The pulse density signal generator may also include rate transition circuits for ensuring that the pulse density input signals and the feedback pulse density signals are uncorrelated.

Disclosed are methods and devices, among which is a device that includes a finite state machine lattice. The lattice may includes a programmable Boolean logic cell that may be programmed to perform various logic functions on a data stream. The programmability includes an inversion of a first input to the Boolean logic cell, an inversion of a last output of the Boolean logic cell, and a selection of an AND gate or an OR gate as a final output of the Boolean logic cell. The Boolean logic cell also includes end of data circuitry configured to cause the Boolean logic cell to only output after an end of data signifying the end of a data stream is received at the Boolean logic cell.

A device including an array of superconducting logic cells, where each of the superconducting logic cells is configured to receive at least one input and provide at least one output, is provided. Each of the superconducting logic cells includes at least one Josephson junction, whose state changes based on at least a biasing condition caused by a phase of a first clock or a phase of a second clock. The array of the superconducting logic cells is configured to perform at least one operation based at least on a connection arrangement of the array of the superconducting logic cells.