A logic cell for a programmable logic integrated circuit apparatus includes a K-input lookup table (LUT) circuit having a primary output Y, wherein Y is any function of K inputs, and at least one additional output (F). A carry circuit receives the outputs of the LUT and a carry-in input CI. The carry circuit generates a sum output S and a carry-out output CO. The carry circuit can be configured to provide S=CI and select CO from the set {0, 1, F}. The carry circuit can alternatively be configured to provide S=EXOR(Y, CI) and select CO from the set {0, 1, F}. The carry circuit can alternatively be configured to provide S=EXOR(Y, CI) and CO=CI if Y=q or to select CO from the set {0, 1, F} if Y≠q, where q is a pre-determined value (e.g., such as 0 or 1).

The application provides a field programmable gate array (FPGA) and a communication method. At least one application specific integrated circuit based (ASIC-based) hard core is embedded in the FPGA. The ASIC-based hard core includes a high-speed exchange and interconnection unit and at least one station. Each station is connected to the high-speed exchange and interconnection unit. The station is configured to transmit data between each functional module in the FPGA and the ASIC-based hard core. The high-speed exchange and interconnection unit is configured to transmit data between the stations. In the FPGA provided by the application, an ASIC-based hard core is embedded, which can facilitate data exchange between each functional module and the ASIC-based hard core in proximity and reduce a time delay.

The application provides a field programmable gate array (FPGA) and a communication method. At least one application specific integrated circuit based (ASIC-based) hard core is embedded in the FPGA. The ASIC-based hard core includes a high-speed exchange and interconnection unit and at least one station. Each station is connected to the high-speed exchange and interconnection unit. The station is configured to transmit data between each functional module in the FPGA and the ASIC-based hard core. The high-speed exchange and interconnection unit is configured to transmit data between the stations. In the FPGA provided by the application, an ASIC-based hard core is embedded, which can facilitate data exchange between each functional module and the ASIC-based hard core in proximity and reduce a time delay.

A method for real-time firmware configuration and a debugging apparatus are provided. When a demand for updating or debugging a target processor raises, in the method, a computer system generates a firmware debugging request that is attached with a firmware data with a specific debugging function. The computer system then loads the firmware data to a programmable logic unit of the debugging apparatus. After the real-time firmware configuration is completed, the computer system issues a debugging command to the programmable logic unit. The programmable logic unit obtains at least one debugging action after resolving the debugging command. The at least one debugging action is performed in the target processor when the target processor receives the at least one debugging action. A debugging result is returned after the at least one debugging action is completed.

A method for real-time firmware configuration and a debugging apparatus are provided. When a demand for updating or debugging a target processor raises, in the method, a computer system generates a firmware debugging request that is attached with a firmware data with a specific debugging function. The computer system then loads the firmware data to a programmable logic unit of the debugging apparatus. After the real-time firmware configuration is completed, the computer system issues a debugging command to the programmable logic unit. The programmable logic unit obtains at least one debugging action after resolving the debugging command. The at least one debugging action is performed in the target processor when the target processor receives the at least one debugging action. A debugging result is returned after the at least one debugging action is completed.

The present invention provides a power efficient content-addressable memory (CAM) architecture that is implementable on FPGAs. The provided CAM architecture comprises an array of CAM cells having a width C.sub.W and a depth C.sub.D, and being grouped into a B number of memory banks. Each of the CAM cells is configured for storing a memory bit and comprises a plurality of flip-flops configured to store at least a masking bit indicating the ternary nature of the stored memory bit and a storing bit saving the binary information of the stored memory bit. The provided CAM architecture allows activating only one bank in multiple banks irrespective of nature of the data set and is updated in a single access and saves power consumption by only accessing the memory in the activated bank. The dynamic power consumption is reduced by 40% compared with the state-of-the-art FPGA-based CAMs.

The present invention provides a power efficient content-addressable memory (CAM) architecture that is implementable on FPGAs. The provided CAM architecture comprises an array of CAM cells having a width C.sub.W and a depth C.sub.D, and being grouped into a B number of memory banks. Each of the CAM cells is configured for storing a memory bit and comprises a plurality of flip-flops configured to store at least a masking bit indicating the ternary nature of the stored memory bit and a storing bit saving the binary information of the stored memory bit. The provided CAM architecture allows activating only one bank in multiple banks irrespective of nature of the data set and is updated in a single access and saves power consumption by only accessing the memory in the activated bank. The dynamic power consumption is reduced by 40% compared with the state-of-the-art FPGA-based CAMs.

Devices, systems and methods for improving a decoding operation in a non-volatile memory are described. An example method includes performing a first hard read to obtain a first set of values stored in a plurality of cells, storing the first set of values in a first buffer, performing a plurality of subsequent hard reads on the plurality of cells to obtain a plurality of subsequent sets of values, performing, for each subsequent set of values, the following operations: computing a quality metric, storing, in a second buffer, a difference between the subsequent set of values and the set of values stored in the first buffer, wherein the difference is stored in a compressed format, and storing, in response to the quality metric exceeding a threshold, the subsequent set of values in the first buffer, and generating, based on the first buffer and the second buffer, the log-likelihood ratio.

Devices, systems and methods for improving a decoding operation in a non-volatile memory are described. An example method includes performing a first hard read to obtain a first set of values stored in a plurality of cells, storing the first set of values in a first buffer, performing a plurality of subsequent hard reads on the plurality of cells to obtain a plurality of subsequent sets of values, performing, for each subsequent set of values, the following operations: computing a quality metric, storing, in a second buffer, a difference between the subsequent set of values and the set of values stored in the first buffer, wherein the difference is stored in a compressed format, and storing, in response to the quality metric exceeding a threshold, the subsequent set of values in the first buffer, and generating, based on the first buffer and the second buffer, the log-likelihood ratio.

Systems and methods are provided for performing error recovery using LLRs generated from multi-read operations. A method may comprise selecting a set of decoding factors for a multi-read operation to read a non-volatile storage device multiple times. The set of decoding factors may include an aggregation mode for aggregating read results of multiple reads. The method may further comprise issuing a command to the non-volatile storage device to read user data according to the set of decoding factors, generating a plurality of Log-Likelihood Ratio (LLR) values using a mapping engine from a pre-selected set of LLR value magnitudes based on the set of decoding factors, obtaining an aggregated read result in accordance with the aggregation mode and obtaining an LLR value from the plurality of LLR values using the aggregated read result as an index.