A timer circuit switches a second changeover switch and a third changeover switch to a pulse output unit for a certain period of time when power supply is started, and causes the pulse output unit to output a code pulse to a second communication line. An input-output control unit switches a first changeover switch to a first terminal for the certain period of time when the power supply is started, determines whether a code indicated by the code pulse received from the first terminal is a regular code, and cuts off electric power supplied from a first power supply line to a second power supply line when the code is not the regular code.

A circuit portion comprising a clock domain is disclosed. A first clock is arranged to clock components in the clock domain. An analogue to digital converter is clocked by a second clock with a duty cycle. The second clock is derived from the first clock. The analogue to digital converter is arranged to output a feedback signal upon finishing a conversion of a sample, and the feedback signal is arranged to control the duty cycle.

The present disclosure relates to a memory device for correcting a pulse duty ratio and a memory system including the same, and relates to a memory device which corrects the duty ratio of a primary pulse of a memory device control signal, and a memory system including the same.

The application provides a field programmable gate array (FPGA) and a communication method. At least one application specific integrated circuit based (ASIC-based) hard core is embedded in the FPGA. The ASIC-based hard core includes a high-speed exchange and interconnection unit and at least one station. Each station is connected to the high-speed exchange and interconnection unit. The station is configured to transmit data between each functional module in the FPGA and the ASIC-based hard core. The high-speed exchange and interconnection unit is configured to transmit data between the stations. In the FPGA provided by the application, an ASIC-based hard core is embedded, which can facilitate data exchange between each functional module and the ASIC-based hard core in proximity and reduce a time delay.

An integrated circuit is provided, including a first latch circuit, a second latch circuit, and a clock circuit. The first latch circuit transmits multiple data signals to the second latch circuit through multiple first conductive lines disposed on a front side of the integrated circuit. The clock circuit transmits a first clock signal and a second clock signal to the first latch circuit and the second latch circuit through multiple second conductive lines disposed on a backside, opposite of the front side, of the integrated circuit.

A method for programming an FPGA, wherein a library, which includes elementary operations and a particular latency table for each of the elementary operations of the library is provided. Each latency table indicates the latency of the particular operation for a plurality of clock rates of the FPGA and for a plurality of input bit widths of the particular operation during the execution on the FPGA, depending on the input bit width of the particular operation and the clock rate of the FPGA. A data path indicating a consecutive execution of at least two elementary operations of the library on the FPGA is defined. The latencies given for the particular input bit width of the particular elementary operations of the data path for a plurality of different clock rates in the latency tables are detected and added, then one of the clock rates is selected.

A three dimensional circuit system includes first and second integrated circuit (IC) dies. The first IC die includes programmable logic circuits arranged in sectors and first programmable interconnection circuits having first router circuits. The second IC die includes non-programmable circuits arranged in regions and second programmable interconnection circuits having second router circuits. Each of the regions in the second IC die is vertically aligned with at least one of the sectors in the first IC die. Each of the second router circuits is coupled to one of the first router circuits through a vertical die-to-die connection. The first and second programmable interconnection circuits are programmable to route signals between the programmable logic circuits and the non-programmable circuits through the first and second router circuits. The circuit system may include additional IC dies. The first and second IC dies and any additional IC dies are coupled in a vertically stacked configuration.

A reliable multi-information entropy PUF for Internet of Things security includes a control circuit, a data register, 128 glitch generation circuits, a 128-to-1 multiplexer, and a Schmidt glitch sampling module. The control circuit controls the data register to generate a square signal, the 128 glitch generation circuits to generate glitch signals to be output and the 128-to-1 multiplexer to select the glitch signals to be output. The Schmidt glitch sampling module samples the glitch signals to obtain PUF response outputs. Each glitch generation circuit generates a glitch signal by means of a fully symmetrical structure. The Schmidt glitch sampling module comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a buffer module and a D flip-flop.

A communications system includes: a control device; a standard proxy input/output circuit configured to control a standard electric device; and an extension proxy input/output circuit configured to control an extension electric device. The control device and the standard proxy input/output circuit are provided on one substrate, and the control device and the extension proxy input/output circuit are connected to each other via an electric wire.

A method, system, and related component for detecting properness of a PG pin power-on timing sequence are provided. The method comprises: obtaining a pull-up level of a PG pin of a VR chip (S101); determining a value of a pull-up resistor of the PG pin, as a first resistance, when a current injected into the VR chip by using the pull-up level is equal to a maximum withstand current of the VR chip (S102); obtaining an equivalent resistance to ground when the PG pin is at a low level, and calculating, based on the equivalent resistance to ground, a value of the pull-up resistor of the PG pin, as a second resistance, when an output voltage of the PG pin is equal to a preset interference voltage limit value (S103); and outputting first prompt information when it is determined that an actual resistance of the pull-up resistor is lower than the first resistance or the second resistance (S104). The foregoing solution is applied, to determine whether a power-on timing sequence of PG pins in a VR chip is proper, thereby avoiding an incorrect action of a subsequent circuit.