Provided are a method of dynamically configuring a FPGA and a network security device. The network security device includes a CPU and at least one FPGA coupled with the CPU. The CPU generates a configuration entry for a target FPGA in response to a user instruction. The configuration entry includes a classification number and a configuration content for the target FPGA. The CPU sends the configuration entry to each FPGA coupled with the CPU, Each FPGA obtains its own classification number, compares its own classification number with the classification number in the configuration entry, and stores the configuration content when the own classification number the same with the classification number in the configuration entry.

An FPGA virtualization platform including a network controller configured to provide an interface to an external network; a static logic section coupled to the network controller, and one or more reconfigurable regions each having a virtualized field programmable gate array vFPGA) that includes a wrapper and a user design.

Disclosed are a self-adaptive chip (100) and configuration method. The self-adaptive chip includes: a plurality of dynamically reconfigurable cells arranged in an array, each of the plurality of dynamically reconfigurable cells being capable of being dynamically reconfigured as needed to execute different operating functions and/or input-output control functions, wherein, each of the plurality of dynamically reconfigurable cells is connected to multiple neighboring dynamically reconfigurable cells, to acquire data from one or more of the multiple neighboring dynamically reconfigurable cells, and output an operation result based on the data to at least one neighboring dynamically reconfigurable cell.

Disclosed are a self-adaptive chip (100) and configuration method. The self-adaptive chip includes: a plurality of dynamically reconfigurable cells arranged in an array, each of the plurality of dynamically reconfigurable cells being capable of being dynamically reconfigured as needed to execute different operating functions and/or input-output control functions, wherein, each of the plurality of dynamically reconfigurable cells is connected to multiple neighboring dynamically reconfigurable cells, to acquire data from one or more of the multiple neighboring dynamically reconfigurable cells, and output an operation result based on the data to at least one neighboring dynamically reconfigurable cell.

A router is used to produce a first integrated circuit structure according to an engineering change order. An initial detail routing topology is imported for the first integrated circuit structure. An engineering change order is received instructing the router to change a portion of the initial detail routing topology for the first integrated circuit structure. A global routing operation is performed which routes global wires for the portion of the initial detail routing topology for the first integrated circuit structure. For each global wire which is routed, a specific global wiring track is selected for the global wire within each edge of a set of global tiles in a routing topology for the first integrated circuit.

A router is used to produce a first integrated circuit structure according to an engineering change order. An initial detail routing topology is imported for the first integrated circuit structure. An engineering change order is received instructing the router to change a portion of the initial detail routing topology for the first integrated circuit structure. A global routing operation is performed which routes global wires for the portion of the initial detail routing topology for the first integrated circuit structure. For each global wire which is routed, a specific global wiring track is selected for the global wire within each edge of a set of global tiles in a routing topology for the first integrated circuit.

A circuit for routing data in an integrated circuit device is described. The circuit comprises an input/output port; an interface circuit coupled to the input/output port and configured to receive data, the interface circuit comprising a selection circuit enabling the selection of the data and a predetermined value; and a control circuit coupled to control the selection circuit; wherein the control circuit holds the input/output port at the predetermined value during a partial reconfiguration of the integrated circuit device in response to a control signal. A method of configuring a circuit for routing data in an integrated circuit device is also described.

Systems and methods for generating and deploying integrated circuit (IC) applications are provided. Partial reconfiguration functionality of an IC may be used to build reconfigurable application platforms that enable application execution on the IC. These apps may include partial reconfiguration bitstreams that allow ease of access to programming without cumbersome compilation via a set of complex tools. The apps may be acquired via a purchasing website or other mechanism, where the bitstreams may be downloaded to the IC, thus increasing usability of the IC as well providing addition revenue streams.

A method for allocating field-programmable gate array (FPGA) resources includes monitoring a first operating metric for one or more computing devices, identifying a first portion of plurality of macro components of a set of one or more FPGA devices in the one or more computing devices, where the first portion is allocated for implementing one or more user defined functions. The method also includes, in response to a first change in the first operating metric, reallocating the first portion of the macro components for implementing a system function associated with the first operating metric, and generating a first notification indicating the reallocation of the first portion.

Provided are a reconfigurable processor and a method of operating the same, the reconfigurable processor including: a configurable memory configured to receive a task execution instruction from a control processor; and a plurality of reconfigurable arrays, each configured to receive configuration information from the configurable memory, wherein each of the plurality of reconfigurable arrays simultaneously executes a task based on the configuration information.