Systems and methods for generating and deploying integrated circuit (IC) applications are provided. Partial reconfiguration functionality of an IC may be used to build reconfigurable application platforms that enable application execution on the IC. These apps may include partial reconfiguration bitstreams that allow ease of access to programming without cumbersome compilation via a set of complex tools. The apps may be acquired via a purchasing website or other mechanism, where the bitstreams may be downloaded to the IC, thus increasing usability of the IC as well providing addition revenue streams.

Aspects of the disclosure are directed to sequencing. In accordance with one aspect, sequencing includes creating a one hot list; selecting a current word of the one hot list as a one hot list output; comparing the one hot list output with a current accumulation register value of an accumulation register to produce a logical comparison; inputting the logical comparison to the accumulation register to generate an updated accumulation register value; and outputting the updated accumulated register state to a client unit to enable or disable the client unit.

A reconfigurable device-based programmable wiring system includes switches. A total number of switches is based on a total number of peripheral terminals and a total number of microcontroller pins. The total number of switches is based on a product of a total number of peripheral terminals and a total number of microcontroller pins. The reconfigurable device-based programmable wiring system includes multiple microcontroller peripherals

A reconfigurable device-based programmable wiring system includes switches. A total number of switches is based on a total number of peripheral terminals and a total number of microcontroller pins. The total number of switches is based on a product of a total number of peripheral terminals and a total number of microcontroller pins. The reconfigurable device-based programmable wiring system includes multiple microcontroller peripherals

An integrated circuit includes first circuits that are configured to implement a user design for the integrated circuit, second circuits that are unused by the user design, and configuration circuitry that couples the second circuits together through a network of conductors. Transistors in the second circuits turn on and off in response to a varying signal that propagates through the second circuits and through the network of conductors while the first circuits implement the user design.

Aspects of the disclosure are directed to sequencing. In accordance with one aspect, sequencing includes creating a one hot list; selecting a current word of the one hot list as a one hot list output; comparing the one hot list output with a current accumulation register value of an accumulation register to produce a logical comparison; inputting the logical comparison to the accumulation register to generate an updated accumulation register value; and outputting the updated accumulated register state to a client unit to enable or disable the client unit.

Disclosed are a self-adaptive chip (100) and configuration method. The self-adaptive chip includes: a plurality of dynamically reconfigurable cells arranged in an array, each of the plurality of dynamically reconfigurable cells being capable of being dynamically reconfigured as needed to execute different operating functions and/or input-output control functions, wherein, each of the plurality of dynamically reconfigurable cells is connected to multiple neighboring dynamically reconfigurable cells, to acquire data from one or more of the multiple neighboring dynamically reconfigurable cells, and output an operation result based on the data to at least one neighboring dynamically reconfigurable cell.

A control system that is reconfigurable during operation comprises a master controller which generates a bit stream, including reconfiguration information, according to the command of a user.The first slave controller comprises: a first dynamic reconfiguration module, which is a field programmable gate array (FPGA) reconfigured according to the reconfiguration information, and which calculates a control value; a static reconfiguration module which is an FPGA controlling the operation of a target apparatus according to the control value; and a control unit reconfiguring one or more of the first dynamic reconfiguration module and the static reconfiguration module according to the reconfiguration information.

A router is used to produce a first integrated circuit structure according to an engineering change order. An initial detail routing topology is imported for the first integrated circuit structure. An engineering change order is received instructing the router to change a portion of the initial detail routing topology for the first integrated circuit structure. A global routing operation is performed which routes global wires for the portion of the initial detail routing topology for the first integrated circuit structure. For each global wire which is routed, a specific global wiring track is selected for the global wire within each edge of a set of global tiles in a routing topology for the first integrated circuit.

Aspects of the disclosure are directed to sequencing. In accordance with one aspect, sequencing includes creating a one hot list; selecting a current word of the one hot list as a one hot list output; comparing the one hot list output with a current accumulation register value of an accumulation register to produce a logical comparison; inputting the logical comparison to the accumulation register to generate an updated accumulation register value; and outputting the updated accumulated register state to a client unit to enable or disable the client unit.