A fuel system includes an electronic control module (ECM), at least one injector coupled to the ECM, and a configurable output driver circuit coupled to the at least one injector. The configurable output driver circuit includes a channel that enables adaptation of ECM outputs. The configurable output driver circuit is configurable based on a value stored in a register circuit.

A method and flow for implementing a “clock tree” inside an ASIC using Sub-threshold or Near-threshold technology with optimal power. The invention may also implement concurrently use of two voltage domains inside a single place and route block. One voltage domain for the “clock tree” buffers and one voltage domain for the other cells at the block. The voltage domain for the “clock tree” buffers that is used is slightly higher than the voltage domain which is used for the other cells. The higher voltage ensures a large reduction of the total number of buffers inside the “clock tree” and the dynamic and static power are reduced dramatically despite the use of slightly higher operating voltage.

A semiconductor device, able to be selectively configured to perform one or more user defined logic functions, includes a semiconductor die and a selectable power regulator. The semiconductor die, in one aspect, includes a first region and a second region. The first region is operatable to perform a first set of logic functions based on a first power domain having a first voltage. The second region is configured to perform a second set of logic functions based on a second power domain having a second voltage. The selectable power regulator, in one embodiment, provides the second voltage for facilitating the second power domain in the second region of the semiconductor die in response to at least one enabling input from the first region of the semiconductor die.

A semiconductor device, able to be selectively configured to perform one or more user defined logic functions, includes a semiconductor die and a selectable power regulator. The semiconductor die, in one aspect, includes a first region and a second region. The first region is operatable to perform a first set of logic functions based on a first power domain having a first voltage. The second region is configured to perform a second set of logic functions based on a second power domain having a second voltage. The selectable power regulator, in one embodiment, provides the second voltage for facilitating the second power domain in the second region of the semiconductor die in response to at least one enabling input from the first region of the semiconductor die.

A transmitter includes a multiplexer, control logic and a voltage mode driver. The multiplexer generates a plurality of time-interleaved data signals based on a plurality of input data signals and multi-phase clock signals. The plurality of input data signals are input in parallel. Each of the plurality of input data signals is a binary signal and has two voltage levels that are different from each other. The control logic generates at least one pull-down control signal and a plurality of pull-up control signals based on the plurality of time-interleaved data signals. Each of the plurality of pull-up control signals has a voltage level that is temporarily boosted. The voltage mode driver generates an output data signal based on the at least one pull-down control signal and the plurality of pull-up control signals. The output data signal is a duobinary signal and has three voltage levels that are different from each other.

A transmitter includes a multiplexer, control logic and a voltage mode driver. The multiplexer generates a plurality of time-interleaved data signals based on a plurality of input data signals and multi-phase clock signals. The plurality of input data signals are input in parallel. Each of the plurality of input data signals is a binary signal and has two voltage levels that are different from each other. The control logic generates at least one pull-down control signal and a plurality of pull-up control signals based on the plurality of time-interleaved data signals. Each of the plurality of pull-up control signals has a voltage level that is temporarily boosted. The voltage mode driver generates an output data signal based on the at least one pull-down control signal and the plurality of pull-up control signals. The output data signal is a duobinary signal and has three voltage levels that are different from each other.

A semiconductor device, able to be selectively configured to perform one or more user defined logic functions, includes a semiconductor die and a selectable power regulator. The semiconductor die, in one aspect, includes a first region and a second region. The first region is operatable to perform a first set of logic functions based on a first power domain having a first voltage. The second region is configured to perform a second set of logic functions based on a second power domain having a second voltage. The selectable power regulator, in one embodiment, provides the second voltage for facilitating the second power domain in the second region of the semiconductor die in response to at least one enabling input from the first region of the semiconductor die.

A semiconductor device, able to be selectively configured to perform one or more user defined logic functions, includes a semiconductor die and a selectable power regulator. The semiconductor die, in one aspect, includes a first region and a second region. The first region is operatable to perform a first set of logic functions based on a first power domain having a first voltage. The second region is configured to perform a second set of logic functions based on a second power domain having a second voltage. The selectable power regulator, in one embodiment, provides the second voltage for facilitating the second power domain in the second region of the semiconductor die in response to at least one enabling input from the first region of the semiconductor die.

Circuit for wake-up receivers are provide. In some embodiments, the wake-up receivers include self-mixers that receive a gate bias voltage. Some of the self-mixers are single ended and some are differential. In some embodiments, the wake-up receivers include a matching network that is connected to the input of the self-mixer. In some embodiments, the wake-up receivers include a low frequency path connected to the output of the self-mixer. In some embodiments, the wake-up receivers include a high frequency path connected to the output of the self-mixer. In some embodiments, the wake-up receivers are configured to receive an encoded bit stream. In some embodiments, the wake-up receivers are configured to wake-up another receiver.

Circuit for wake-up receivers are provide. In some embodiments, the wake-up receivers include self-mixers that receive a gate bias voltage. Some of the self-mixers are single ended and some are differential. In some embodiments, the wake-up receivers include a matching network that is connected to the input of the self-mixer. In some embodiments, the wake-up receivers include a low frequency path connected to the output of the self-mixer. In some embodiments, the wake-up receivers include a high frequency path connected to the output of the self-mixer. In some embodiments, the wake-up receivers are configured to receive an encoded bit stream. In some embodiments, the wake-up receivers are configured to wake-up another receiver.