A delay locked loop circuit includes a first delay locked loop and a second delay locked loop having different characteristics. The first delay locked loop performs a delay-locking operation on a reference clock signal to generate a delay locked clock signal. The second delay locked loop performs a delay-locking operation on the delay locked clock signal to generate an internal clock signal.

A phase calibration method includes sweeping phase codes applicable to a serial clock signal, identifying a first, a second, a third, and a fourth phase code, wherein the first phase code causes zero plus a first threshold number of bits extracted from the serial data signal to be a particular value, wherein the second phase code causes all minus a second threshold number of bits extracted from the serial data signal to be the particular value, wherein the third phase code causes all minus a third threshold number of bits extracted from the serial data signal to be the particular value, wherein the fourth phase code causes zero plus a fourth threshold number of bits extracted from the serial data signal to be the particular value, determining an average phase code based on the identified phase codes.

The present disclosure relates to the technical field of integrated circuits, and specifically to a delay-locked loop, a control method for a delay-locked loop, and an electronic device. The delay-locked loop includes: a secondary path configured to perform frequency division on an input clock signal to generate a frequency-divided clock signal, adjust the frequency-divided clock signal having a first frequency to obtain an output clock signal in a locking process of the delay-locked loop, and adjust the frequency-divided clock signal to make the frequency-divided clock signal have a second frequency when the delay-locked loop is locked in a standby state, wherein the second frequency is lower than the first frequency; and a primary path configured to output, when obtaining a target instruction, an output clock replica signal having a same phase as the output clock signal.

An apparatus has a plurality of multi-level comparison circuits, each coupled to a pair of wires in a three-wire communication link, a plurality of first-level clock recovery circuits and a second-level clock recovery circuit. Each multi-level comparison circuit provides a multibit signal as an output. Each first-level clock recovery circuit includes a plurality of first-level flipflops clocked by transitions in a multibit signal received from one multi-level comparison circuit of the plurality of multi-level comparison circuits, and a first delay circuit that delays an output of the each first-level clock recovery circuit to provide a first reset signal that resets the each first-level clock recovery circuit. The second-level clock recovery circuit includes a second-level flipflop clocked by transitions in the outputs of the plurality of first-level clock recovery circuits, and a second delay circuit that delays an output of the second-level clock recovery circuit to provide a second reset signal to the second-level flipflop.

An electronic device includes a dock dividing circuit configured to generate sampling clocks, alignment clocks and output clocks by dividing a frequency of a write clock; and a data alignment circuit configured to, in a first operation mode, receive input data having any one level among a first level to a fourth level and generate alignment data by aligning the input data in synchronization with the sampling clocks, the alignment clocks and the output clocks, and to, in a second operation mode, receive the input data having any one level of the first level and the fourth level and generate the alignment data by aligning the input data in synchronization with the sampling clocks, the alignment clocks and the output clocks.

In a phase adjustment circuit, a binary circuit is configured to output a binary signal on the basis of an edge of a video signal. A phase-delayed clock signal generation circuit is configured to generate a phase-delayed clock signal having a later phase than a phase of a clock signal by a first delay amount. A delay time control circuit is configured to cause a phase of the binary signal and the phase of the phase-delayed clock signal to match each other by adjusting the first delay amount. A sampling signal generation circuit is configured to generate a sampling signal having a later phase than the phase of the clock signal by a second delay amount. The second delay amount is in accordance with both a phase shift amount, which is based on the clock signal, and the first delay amount.

A system delays input clock signals using time-to-digital converters (TDCs) to convert edges or the clock signals to digital values and storing the digital values in a memory. The digital values are retrieved from the memory based on a desired delay. A time counter used by the TDCs to determine the edges is also used determine the delay. The accuracy and range of the delay depends on the time counter and size of the memory.

Methods and devices for determining integrated circuit (IC) device degradation over time are provided. Transistors are the basic building blocks of IC devices. The degradation of the transistors in IC devices over time leads slowly to decreased switching speeds. To monitor the condition of an IC device as it ages, oscillator circuitry operating at switching frequencies of various circuits in the IC device may be included and monitored for changes in switching frequency over time. A degraded condition of the IC device may be determined when the change in switching frequency exceeds a threshold value.

A memory controller includes a clock signal generator generating a clock signal; a first data receiving circuit receiving a serial signal having a plurality of logic values from a memory, using the serial signal to compensate for a phase error of the clock signal, and generating a phase-compensated clock signal as a first clock signal; and at least one second data receiving circuit receiving data from the memory, receiving the first clock signal from the first data receiving circuit, and using the first clock signal to recover the data.

A method includes determining a phase error for a first clock signal and a second clock signal and determining an offset based on the phase error for the first clock signal and the second clock signal. The method also includes adding the offset to a phase of the first clock signal to produce a first adjusted clock signal and subtracting the offset from a phase of the second clock signal to produce a second adjusted clock signal. A phase error for the first adjusted clock signal and the second adjusted clock signal is smaller than the phase error for the first clock signal and the second clock signal.