A divider-less fractional digital phase locked loop (PLL) is disclosed and can include a time-to-digital converter (TDC) to receive a reference clock signal and a digitally control oscillator (DCO) clock signal, and generate a phase difference signal based on the reference clock signal and the DCO clock signal. A counter coupled in parallel to the TDC can receive the clock signal and count an output frequency of the clock signal to detect reference noise within the reference signal that is above a threshold. A sampler can sample an output of the counter using a replica of the reference signal, and generate a plurality of samples. A sample selector can select one of the plurality of samples based on the phase difference signal. A digital phase detector (DPD) can generate an output phase measurement based on the phase difference signal and the selected sample of the plurality of samples.

A phase locked loop circuit is disclosed. The phase locked loop circuit includes a ring oscillator. The phase locked loop circuit also includes a digital path including a digital phase detector. The phase locked loop circuit further includes an analog path including a linear phase detector. Additionally, the phase locked loop circuit includes a feedback path connecting an output of the ring oscillator to an input of the digital path and an input of the analog path. The digital path and the analog path are parallel paths. The digital path provides a digital tuning signal the ring oscillator that digitally controls a frequency of the ring oscillator. The analog path provides an analog tuning signal the ring oscillator that continuously controls the frequency of the ring oscillator.

Described embodiments include a system, including clocked circuitry, an oscillator controller, and an oscillator, configured to output an output clock signal that clocks the clocked circuitry and is fed to the oscillator controller. The oscillator controller is configured to control the oscillator responsively to an output frequency of the output clock signal. The system further includes power-management circuitry, configured to cause the clocked circuitry to sleep by disabling the oscillator, and waking circuitry, configured to intermittently enable the oscillator such that the oscillator controller intermittently, while the clocked circuitry sleeps, causes the output frequency to converge to a target frequency by controlling the oscillator. Other embodiments are also described.

Systems and methods are described for determining a phase measurement difference between a received modulated signal and a local clock signal. An adjusted local clock phase measurement may be determined by subtracting, from the phase measurement difference, a phase correction that is based on the frequency difference between the modulator signal's carrier frequency and the local clock's frequency. A phase modulation value may be generated by scaling the adjusted local clock phase measurement. The scaling may be based on a ratio of the modulated signal's carrier frequency and the local clock's frequency. The phase correction may be based on (i) a count of periods of the modulated signal occurring between each corrected phase measurement and (ii) a difference between the carrier frequency and the local clock frequency.

A phase locked loop circuit is disclosed. The phase locked loop circuit includes a ring oscillator. The phase locked loop circuit also includes a digital path including a digital phase detector. The phase locked loop circuit further includes an analog path including a linear phase detector. Additionally, the phase locked loop circuit includes a feedback path connecting an output of the ring oscillator to an input of the digital path and an input of the analog path. The digital path and the analog path are parallel paths. The digital path provides a digital tuning signal the ring oscillator that digitally controls a frequency of the ring oscillator. The analog path provides an analog tuning signal the ring oscillator that continuously controls the frequency of the ring oscillator.

In one embodiment, the voltage droop monitoring circuit includes a ring oscillator circuit block configured to generate a plurality of oscillation signals and configured to output a selected oscillation signal from one of the plurality of oscillation signals based on a first control signal. The first control signal is based on a power supply voltage of a functional circuit block. The voltage droop monitoring circuit further includes a counter configured to generate a count value based on the selected oscillation signal, and a droop detector configured detect droop in the power supply voltage of the functional circuit block based on the count value and at least one threshold value.

A locked loop circuit is disclosed. The locked loop circuit includes phase detection circuitry to generate a first error output based on a phase difference between a first reference input and a locked-loop output. Summing circuitry receives the first error output and a second error signal. The second error signal is based on one from a selection of error values. Oscillator/delay circuitry generates the locked-loop output. For a first mode of operation, the second error signal is based on a first selected error value. For a second mode of operation, the second error signal is based on a second selected error value different than the first selected error value.

Methods, systems, and devices for section-based data protection in a memory device are described. In one example, a memory device may include a set memory sections each having memory cells configured to be selectively coupled with access lines of the respective memory section. A method of operating the memory device may include selecting at least one of the sections for a voltage adjustment operation based on a determined value of a timer, and performing the voltage adjustment operation on the selected section by activating each of a plurality of word lines of the selected section. The voltage adjustment operation may include applying an equal voltage to opposite terminals of the memory cells, which may allow built-up charge, such as leakage charge accumulating from access operations of the selected memory section, to dissipate from the memory cells of the selected section.

A phase locked loop circuit is disclosed. The phase locked loop circuit includes a ring oscillator. The phase locked loop circuit also includes a digital path including a digital phase detector. The phase locked loop circuit further includes an analog path including a linear phase detector. Additionally, the phase locked loop circuit includes a feedback path connecting an output of the ring oscillator to an input of the digital path and an input of the analog path. The digital path and the analog path are parallel paths. The digital path provides a digital tuning signal the ring oscillator that digitally controls a frequency of the ring oscillator. The analog path provides an analog tuning signal the ring oscillator that continuously controls the frequency of the ring oscillator.

Time measuring circuitry has a ring oscillator, a time-to-digital converter, a time measurer and a phase randomizer. The ring oscillator has a plurality of delay circuitries connected in a ring shape, the ring oscillator adjusting delay times of the plurality of delay circuitries based on an oscillation control signal to generate an oscillation signal. The time-to-digital converter quantizes a phase of the oscillation signal at a transition timing of a reference signal. The phase synchronizing circuitry to generate the oscillation control signal based on an output signal of the time-to-digital converter so that a phase of the oscillation signal coincides with a phase of the reference signal. The time measurer to measure a time interval based on the output signal of the time-to-digital converter. The phase randomizer to randomly shift the phase of the oscillation signal to be locked by the phase synchronizing circuitry.