The operation of the phase-locked loop includes a startup phase where a reference signal having a duty cycle of 50% is applied to a phase comparator of the loop. A first divider of an output signal of the voltage-controlled oscillator of the loop is reset at each first type signal edge of the reference signal. The phase comparator receives the reference signal and a feedback signal from the first divider and generates a control pulse at each second type signal edge of the reference signal that causes a control voltage of the oscillator to increase.

The system includes an intermediate-frequency (IF) synthesizer that generates an IF signal based on a reference signal, and a sub-sampling PLL (SSPLL) that generates a high-frequency output signal based on an input. A switch selects either the reference signal or the IF signal to be the input to the SSPLL. When the reference signal is the input to the SSPLL, the frequency synthesizer operates in a low-noise normal-operating mode, and when the IF signal is the input to the SSPLL, the frequency synthesizer operates in a higher-noise, frequency-acquisition mode. A sub-sampling lock detector (SSLD) determines whether the frequency synthesizer becomes unlocked during the normal-operating mode, and if so, activates the switch to move the system into the frequency-acquisition mode. It also determines whether the frequency synthesizer becomes relocked to the target frequency during the frequency-acquisition mode, and if so, activates the switch to move the system into the normal-operating mode.

In described examples, a feedback loop has phase detection (PD) circuitry that has a reference input to receive a reference frequency signal, a feedback input to receive a feedback signal, and phase difference outputs. A phase to digital converter (P2DC) includes a first phase to charge converter (PCC) that has a gain polarity and a first phase error output; a second PCC that has an opposite gain polarity and a second phase error output. A differential loop filter has an amplifier with an inverting input coupled to the first phase error output and a non-inverting input coupled to the second phase error output. An analog to digital converter (ADC) has an input coupled to an output of the differential loop filter. A feedback path is coupled to the output of the P2DC, with an output of the feedback path providing the feedback signal to the PD feedback input.

A clock generator including a phase frequency detector configured to compare a phase and a frequency of a reference clock signal with a phase and a frequency of a first output clock signal and generate a detection signal based on a difference in the phases and frequencies of the clock signals; a loop filter configured to generate a first control voltage signal based on the detection signal; a first voltage controlled oscillator configured to generate and output a first output clock signal based on the first control voltage signal, a modulation filter configured to generate a modulation voltage signal based on the reference clock signal and generate a second control voltage signal by combining the modulation voltage signal and the first control voltage signal, and a second voltage controlled oscillator configured to generate and output a second output clock signal based on the second control voltage signal is provided.

The present invention provides a clock generating circuit, wherein the clock generating circuit includes a phase detector, an integral path, a proportional path, a bias path and an oscillator. In the operations of the clock generating circuit, the phase detector generates a detection result according to a reference signal and a feedback signal, a first charge pump within the integral path generates a first control signal according to the detection result, a second charge pump within proportional path generates a second control signal according to the detection result, a low-pass filter within the bias path filters the first control signal to generate a third control signal, and the oscillator generates a clock signal according to the first control signal, the second control signal and the third control signal.

The present invention provides a clock generating circuit, wherein the clock generating circuit includes a phase detector, an integral path, a proportional path, a bias path and an oscillator. In the operations of the clock generating circuit, the phase detector generates a detection result according to a reference signal and a feedback signal, a first charge pump within the integral path generates a first control signal according to the detection result, a second charge pump within proportional path generates a second control signal according to the detection result, a low-pass filter within the bias path filters the first control signal to generate a third control signal, and the oscillator generates a clock signal according to the first control signal, the second control signal and the third control signal.

Aspects of this disclosure relate to a VLIF receiver with automatic phase noise adjustment. The presence of an interfering signal is sensed within a bandwidth around a desired channel frequency. Then the local oscillator phase noise is automatically adjusted to optimize blocking. The phase noise adjustment includes increasing the bandwidth of a phase-locked loop.

A spread spectrum clock generation apparatus includes a frequency modulator configured to generate an output clock signal, a frequency of which is variable with reference to a predetermined center frequency, by frequency-modulating an input clock signal according to a modulation profile signal; and a profile generator configured to generate a nested-modulation profile for controlling the frequency of the output clock signal, generate the modulation profile signal according to the nested-modulation profile, and output the modulation profile signal to the frequency modulator, wherein the profile generator is further configured to generate the nested-modulation profile by varying a cycle and a change range of a triangle modulation profile having a triangle waveform pattern having a pre-designated cycle and a pre-designated amplitude with reference to the center frequency in a time-frequency domain.

A physiological information collecting system and a transceiver device thereof are configured to collect physiological information from animal bodies. The transceiver device includes a front-end circuit, a follower circuit, a quadrature delay line and an output circuit. The front-end circuit separates a discontinuous signal into an in-phase signal and a quadrature signal. The follower circuit outputs a control voltage and rotates the in-phase signal by a predetermined phase angle to output a follower signal. The quadrature delay line rotates the quadrature signal by a corresponding phase angle according to the control voltage. The output circuit synthesizes the follower signal and the quadrature signal and outputs a data signal by demodulating the discontinuous signal. Consequently, the transceiver device reduces the bandwidth range of the discontinuous signal when receiving the discontinuous signal, reduces the power consumed by the transceiver device, and demodulates the discontinuous signal with various transmission rates of different data.

A PLL circuit includes a phase comparator, a charge pump 20, a loop filter 30, a voltage controlled oscillator 40, a frequency divider, and a phase compensator 70. The loop filter 30 includes a resistor 31, a first capacitance element 32, and a second capacitance element 33. The phase compensator 70 is provided in parallel to the charge pump 20 and adds a differentiation term to an open-loop transfer function. The phase compensator 70 includes a buffer 71 receiving a phase difference signal output from the phase comparator and a third capacitance element 72 provided between an output terminal of the buffer 71 and an input terminal of the loop filter 30.