A clock synthesizer is provided. The Clock synthesizer includes a a Phase Locked Loop (PLL) configured to generate a clock signal based on a reference signal. A clock buffer is connected to the PLL. The clock buffer is configured to store the clock signal. A Duty Cycle Controller and Phase Interpolator (DCCPI) circuit is connected to the clock buffer. The DCCPI circuit is configured to receive the clock signal from the clock buffer, adjust a duty cycle of the clock signal to substantially equal to 50%, perform phase interpolation on the clock signal, and provide the clock signal as an output after adjusting the duty cycle substantially equal to 50% and performing the phase interpolation.

A clock synthesizer is provided. The Clock synthesizer includes a a Phase Locked Loop (PLL) configured to generate a clock signal based on a reference signal. A clock buffer is connected to the PLL. The clock buffer is configured to store the clock signal. A Duty Cycle Controller and Phase Interpolator (DCCPI) circuit is connected to the clock buffer. The DCCPI circuit is configured to receive the clock signal from the clock buffer, adjust a duty cycle of the clock signal to substantially equal to 50%, perform phase interpolation on the clock signal, and provide the clock signal as an output after adjusting the duty cycle substantially equal to 50% and performing the phase interpolation.

An IQ mixer is used in a Pound-stabilized microwave source to detect amplitude modulation of the signal reflected from the reference resonator. By properly configuring the IQ mixer so that the LO and RF inputs are maintained in quadrature at the Q mixer, hence in-phase at the I mixer, lower levels of amplitude modulation may be detected at lower modulation frequencies compatible with optimal choices of resonator coupling and maximal phase to amplitude conversion. With the Q mixer held in quadrature it acts as a broadband phase noise detector. A portion of the Q mixer output is bandpass filtered and summed with the I mixer Pound-server voltage to achieve both center frequency stabilization and broadband phase noise suppression.

An IQ mixer is used in a Pound-stabilized microwave source to detect amplitude modulation of the signal reflected from the reference resonator. By properly configuring the IQ mixer so that the LO and RF inputs are maintained in quadrature at the Q mixer, hence in-phase at the I mixer, lower levels of amplitude modulation may be detected at lower modulation frequencies compatible with optimal choices of resonator coupling and maximal phase to amplitude conversion. With the Q mixer held in quadrature it acts as a broadband phase noise detector. A portion of the Q mixer output is bandpass filtered and summed with the I mixer Pound-server voltage to achieve both center frequency stabilization and broadband phase noise suppression.

Various implementations described herein are directed to a device with a voltage-controlled oscillator that receives an enable signal, receives a reset signal, and provides internal pulse signals including one or more coarse internal pulse signals and multiple fine internal pulse signals. The device may have a coarse sampler that receives the one or more coarse internal pulse signal and provides a coarse sampled output signal. The device may have a fine sampler that receives the multiple fine internal pulse signals and provides a fine sampled output signal.

Various implementations described herein are directed to a device with a voltage-controlled oscillator that receives an enable signal, receives a reset signal, and provides internal pulse signals including one or more coarse internal pulse signals and multiple fine internal pulse signals. The device may have a coarse sampler that receives the one or more coarse internal pulse signal and provides a coarse sampled output signal. The device may have a fine sampler that receives the multiple fine internal pulse signals and provides a fine sampled output signal.

A method and apparatus for performing on-system phase-locked loop (PLL) management in a memory device are provided. The method may include: utilizing a processing circuit within the memory controller to set multiple control parameters among multiple parameters stored in a register circuit of a transmission interface circuit within the memory controller, for controlling parameter adjustment of a PLL of the transmission interface circuit; utilizing a trimming control circuit to perform the parameter adjustment of the PLL according to the multiple control parameters, to adjust a set of voltage parameters among the multiple parameters, for optimizing a control voltage of a voltage controlled oscillator (VCO); and during the parameter adjustment of the PLL, utilizing the trimming control circuit to generate and store multiple processing results in the register circuit, for being sent back to the processing circuit, to complete the parameter adjustment of the PLL, thereby achieving the on-system PLL management.

A method and apparatus for performing on-system phase-locked loop (PLL) management in a memory device are provided. The method may include: utilizing a processing circuit within the memory controller to set multiple control parameters among multiple parameters stored in a register circuit of a transmission interface circuit within the memory controller, for controlling parameter adjustment of a PLL of the transmission interface circuit; utilizing a trimming control circuit to perform the parameter adjustment of the PLL according to the multiple control parameters, to adjust a set of voltage parameters among the multiple parameters, for optimizing a control voltage of a voltage controlled oscillator (VCO); and during the parameter adjustment of the PLL, utilizing the trimming control circuit to generate and store multiple processing results in the register circuit, for being sent back to the processing circuit, to complete the parameter adjustment of the PLL, thereby achieving the on-system PLL management.

In described examples, a phase locked loop (PLL) has a first phase detector cell (PD) that has a gain polarity. The first PD cell has a phase error output and inputs coupled to a reference frequency signal and a feedback signal. A second PD cell has an opposite gain polarity. The second PD cell has a phase error output and inputs coupled to the reference frequency signal and the feedback signal. A loop filter has a feedforward path and a (lossy) integrating path coupled to an output of the filter. The feedforward path has a third PD cell that has phase error output AC-coupled to the filter output. The integrating path includes an opamp that has an inverting input coupled to the first PD cell phase error output and a non-inverting input coupled to the second PD cell phase error output.

In described examples, a phase locked loop (PLL) has a first phase detector cell (PD) that has a gain polarity. The first PD cell has a phase error output and inputs coupled to a reference frequency signal and a feedback signal. A second PD cell has an opposite gain polarity. The second PD cell has a phase error output and inputs coupled to the reference frequency signal and the feedback signal. A loop filter has a feedforward path and a (lossy) integrating path coupled to an output of the filter. The feedforward path has a third PD cell that has phase error output AC-coupled to the filter output. The integrating path includes an opamp that has an inverting input coupled to the first PD cell phase error output and a non-inverting input coupled to the second PD cell phase error output.