A reference sampling Type-I fractional-N PLL directly samples the reference clock and therefore does not use a reference buffer. Here, a phase-detector is a passive sampling switch which neither consumes any power nor generates any noise. Therefore, all the major contributors of in-band phase-noise are eliminated by the reference sampling Type-I fractional-N divider. A double sampling phase-detector with a switched-capacitor passive voltage interpolator circuit is used to achieve fractional-N output. To achieve a high resolution of the voltage interpolator or the switched capacitor, a sigma-delta modulator is used.

A clock generator comprise a delta-sigma modulation, DSM, for generating a division control signal and a phase control signal, an oscillator, for generating an oscillation signal with a first frequency, an adjustable frequency divider, for performing a division operation on the oscillation signal according to the division control signal, to generate a first division signal and a second division signal with a second frequency, and a phase interpolator, PI, for performing a phase interpolation operation on the first and second division signals according to the phase control signal, to generate an output signal with an output frequency, wherein the first frequency is greater than the second frequency.

A method and apparatus for controlling a frequency range of a self-resonant frequency (SRF) of a high speed divider implemented in current mode logic (CML) D triggers by controlling a field effect transistor (FET) load resistor bias voltage to FETs operating in linear regions in load resistors in the CML D triggers. Tail currents of the CML D triggers are controlled to track inversely to a resistor value.

A method and apparatus for controlling a frequency range of a self-resonant frequency (SRF) of a high speed divider implemented in current mode logic (CML) D triggers by controlling a field effect transistor (FET) load resistor bias voltage to FETs operating in linear regions in load resistors in the CML D triggers. Tail currents of the CML D triggers are controlled to track inversely to a resistor value.

A method of operation in a locked-loop circuit. The locked-loop circuit includes a loop filter and a digitally-controlled oscillator (DCO). The loop filter includes a first input to receive a digital word representing a difference between a reference clock frequency and a DCO output frequency. The loop filter includes internal storage. The method includes selecting a desired DCO output frequency that is generated in response to a calibration DCO codeword. A start value is retrieved from the loop filter internal storage. The start value corresponds to the calibration DCO codeword. The locked-loop circuit is then started with the retrieved start value.

A method of operation in a locked-loop circuit. The locked-loop circuit includes a loop filter and a digitally-controlled oscillator (DCO). The loop filter includes a first input to receive a digital word representing a difference between a reference clock frequency and a DCO output frequency. The loop filter includes internal storage. The method includes selecting a desired DCO output frequency that is generated in response to a calibration DCO codeword. A start value is retrieved from the loop filter internal storage. The start value corresponds to the calibration DCO codeword. The locked-loop circuit is then started with the retrieved start value.

A method of operation in a locked-loop circuit. The locked-loop circuit includes a loop filter and a digitally-controlled oscillator (DCO) coupled to the output of the loop filter. The loop filter includes a first input to receive a digital word representing a difference between a reference clock frequency and a DCO output frequency. The method includes determining a calibration DCO codeword representing a calibration operating point for the locked-loop circuit; determining a scaling factor based on the calibration operating point, the scaling factor based on a ratio of an actual DCO gain to a nominal DCO gain; and applying the scaling factor to operating parameters of the loop filter.

A method of operation in a locked-loop circuit. The locked-loop circuit includes a loop filter and a digitally-controlled oscillator (DCO) coupled to the output of the loop filter. The loop filter includes a first input to receive a digital word representing a difference between a reference clock frequency and a DCO output frequency. The method includes determining a calibration DCO codeword representing a calibration operating point for the locked-loop circuit; determining a scaling factor based on the calibration operating point, the scaling factor based on a ratio of an actual DCO gain to a nominal DCO gain; and applying the scaling factor to operating parameters of the loop filter.

In described examples, a method of operating a transmitter includes generating a frequency reference signal having a reference frequency and outputting the frequency reference to a phase locked loop (PLL) that includes a voltage controlled oscillator (VCO). The VCO output is locked to the frequency reference signal to form a carrier signal. The transmitter receives an I input signal, a Q input signal, and a direct current (DC) leaky carrier signal. Either the I input signal or the Q input signal is added to the leaky carrier signal. The carrier signal is modulated with the resulting two signals using an I-Q mixer to generate a modulated signal that includes an unmodulated carrier signal component. The modulated signal is then transmitted.

In described examples, a method of operating a transmitter includes generating a frequency reference signal having a reference frequency and outputting the frequency reference to a phase locked loop (PLL) that includes a voltage controlled oscillator (VCO). The VCO output is locked to the frequency reference signal to form a carrier signal. The transmitter receives an I input signal, a Q input signal, and a direct current (DC) leaky carrier signal. Either the I input signal or the Q input signal is added to the leaky carrier signal. The carrier signal is modulated with the resulting two signals using an I-Q mixer to generate a modulated signal that includes an unmodulated carrier signal component. The modulated signal is then transmitted.