An apparatus and method for analog-to-digital conversion. The apparatus includes a first analog-to-digital converter (ADC), a second ADC, and a calibration unit. The first ADC is configured to sample an input analog signal at a first sampling frequency. The second ADC is configured to sample the input analog signal at a second sampling frequency. The second sampling frequency is a fraction of the first sampling frequency. The calibration unit is configured to correct a distortion incurred in an output of the first ADC based on an output of the second ADC. The first ADC may be a time-interleaved ADC. The second ADC may be an extra sub-ADC of the time-interleaved ADC. The second ADC may be configured to sample the input analog signal at random sampling phases. A dithering noise may be added to the input analog signal of the second ADC. The calibration unit may be a non-linear equalizer.

An analog-to-digital converting system and a method with offset correction mechanisms are provided. The method includes steps of: obtaining a direct current offset of an output voltage of a digital analog conversion unit in a system; obtaining first capacitance weights and second capacitance weights sequentially from small to large; subtracting the direct current offset from a digital signal; and multiplying bit values of the digital signal respectively by the corresponding first capacitance weight value or second capacitance weight value to output a decode signal.

Differential circuitry including first and second current paths each including a succession of first and further load nodes, each successive further load node connected to its preceding load node via a divider impedance; and first switching circuitry connected to the further load node or nodes of the first current path, and second switching circuitry connected to the further load node or nodes of the second current path, the first and second switching circuitry controlling a magnitude of controllable current signals passing through the load nodes of the first current path and the second current path, respectively, wherein: the first load nodes of the first and second current paths include a first pair of load nodes, and the or each successive further load node of the first current path and its corresponding successive further load node of the second current path include a successive further pair of load nodes.

A power consumption control method for an electronic device, an electronic device, and a storage medium, and the method includes: obtaining a current state of the electronic device; determining a target integration time of an ADC sampling circuit based on the obtained current state; and adjusting an integration time of the ADC sampling circuit to the target integration time, and adjusting a power-on time of a hidden function key based on the adjusted integration time to control actual power consumption of the electronic device, wherein the integration time is positively correlated with the power-on time.

Noise suppression is achieved by averaging a sequence of repetitive waveforms with correction of frequency distortions, establishing a real time processing of signals. First, the waveforms are processed seriatim, and saved in partitioned memory. Then, the memory contents are merged to form an output digital signal. Initially, an input repetitive signal is sampled with a sampling period T, and divided into K sections along the sampling period so that a k.sup.th section, where 0k<K, coincides with segment [k.Math.T/K, (k1).Math.T/K]. Time displacement detection determines relative positions of trigger pulses and edges of the sampling clock, and the number k of a sampling period section where the trigger pulse appears, keeping k unchanged thereafter. A resultant stream of N.Math.K samples is transmitted through a lowpass filter, followed by decimation by K, to complete the averaging.

Described herein are apparatus and methods for realization of time interleaved digital-to-analog converters (DACs) by detecting and aligning phase mismatches. In an implementation, a N-time interleaved DAC includes N DACs and N replica DACs, where a first set of N/2 DACs operate at a clock A and a second set of N/2 DACs operate at a clock B, and where N is at least two. The phase detector generates a phase detection output by comparing outputs of the first and second set of N/2 replica DACs with a multiplexor (MUX) clock, where the MUX clock is a multiple of a frequency of the clock A or the clock B. The clock A and the clock B are aligned with the MUX clock by advancing a phase of the clock A and the clock B until the phase detection output achieves a zero crossing.

An image capturing apparatus is provided. The apparatus comprises a pixel array, a signal generator that generates a comparison signal whose electric potential changes with time and a converter that converts a pixel signal into a digital signal. The comparison signal starts to change from a first electric potential in accordance with a start of the conversion of the pixel signal by the converter, and changes again, in accordance with inversion of a magnitude relationship between the pixel signal and the comparison signal, from a third electric potential between the first electric potential and a second electric potential at which the magnitude relationship is inverted. The converter includes a counter that holds, as a signal value, a count value obtained by counting from the start of the conversion of the pixel signal until the inversion of the magnitude relationship.

It is described an electronic device (1) for measuring an electric quantity, comprising: an analog-digital conversion module (2) configured to digitally convert time portions of an analog signal (S.sub.M(t)) to be measured alternated with time portions of a reference analog signal (S.sub.R(t)), for supplying respective first (D.sub.SM) and second pluralities (D.sub.SR) of digital values and a digital processing module (3) configured to: calculate a first mean amplitude (A1) of the first pluralities of digital values, and a second mean amplitude (A2) of the second pluralities of digital values; the first and second mean amplitudes being proportional to a mean gain value of the analog-digital conversion module (2); supply a ratio value (V.sub.RT) of the first mean amplitude to the second mean amplitude, representative of a measured amplitude of the analog signal (S.sub.M(t)) to be measured.

A self-calibrating Analog-to-Digital Converter (ADC) performs radix error calibration using a Successive-Approximation Register (SAR) to drive test voltages onto lower-significant capacitors. The final SAR code is corrected by performing LSB averaging on LSB averaging capacitors and then accumulated, and the measurement repeated many times to obtain a digital average measurement. An ideal radix or ratio of the measured capacitor's capacitance to a unit capacitance of an LSB capacitor is subtracted from the digital average measurement to obtain a measured error that is stored in a Look-Up Table (LUT) with the ideal radix. Radix error calibration is repeated for other capacitors to populate the LUT. During normal ADC conversion, the SAR code obtained from converting the analog input is applied to addresses the LUT, and all ideal radixes and measured errors for 1 bits in the SAR code are added together to generate an error-corrected digital value.

A method of weight calibration in a DAC (25) is disclosed. The DAC (25) comprises an input port (100) for receiving a sequence of digital input words (x[n]), each representing a digital input sample, and a digital control circuit (110) configured to encode each digital input word (x[n]) into a control word (z[n]) representing the same digital input sample. Each bit (Z.sub.i) in the control word (z[n]) has a corresponding bit weight (w.sub.i) and is in the following considered to adopt values in {?1, 1}. Furthermore, the DAC (25) comprises a set (120) of analog weights, each associated with a unique one of the bits (Z.sub.i) in the control word (z[n]), and summation circuitry (130) configured to generate an analog sample corresponding to the digital input sample by summing the bits in the control word (Z.sub.i) weighted by the respective associated analog weights. The DAC (25) also has an output (140) for outputting the analog sample. The method comprises, during a measurement procedure, for a first set of at least one bit of the control word (z[n]), generating (300) the bits of the first set, such that a first sum of the bits in the first set weighted by their respective bit weights is, on average, above zero. Furthermore, the method comprises, during the measurement procedure, for a second set of at least one bit of the control word (z[n]), generating (310) the bits of the second set, such that a second sum of the bits in the second set weighted by their respective bit weights is, on average, below zero and such that the sum of the first sum and the second sum is, on average, equal to zero. The method also comprises detecting (330) a DC level at the output of the DAC during the measurement procedure. The method further comprises adjusting (340) at least one analog weight in response to the detected DC level. A corresponding DAC, a corresponding electronic apparatus, and a corresponding integrated circuit are also disclosed.