Embodiments of the present invention provide a digital-to-analog conversion circuit, where the digital-to-analog conversion circuit includes a signal amplitude detector and a digital-to-analog converter. When the signal amplitude detector detects a low signal amplitude, a first current module in the digital-to-analog converter operates normally and a second current module in the digital-to-analog converter stops operating. In addition, when stopping operating, the second current module is in a state of a third bias voltage and a fourth bias voltage that are generated by a second bias circuit. When the amplitude detector detects a high signal amplitude subsequently, the second current module resumes normal operation. After operating normally, the second current module switches back to a first bias voltage and a second bias voltage that are generated by a first bias circuit. This reduces a nonlinearity problem caused before a second current module resumes normal operation.

Certain aspects of the present disclosure are directed towards a digital-to-analog converter (DAC) system. The DAC system generally includes a first driver and a plurality of current-steering cells. A first current-steering cell of the plurality of current-steering cells includes: a first current source coupled to a first current-steering transistor and a second current-steering transistor, wherein a gate of the first current-steering transistor and a gate of the second current-steering transistor are coupled to a first output and a second output of the first driver, respectively; a first transistor having a source coupled to a current source path and a drain coupled to a reference potential node; and a second transistor having a source coupled to the current source path and a drain coupled to the reference potential node.

An analog-to-digital converter of non-binary capacitor array with redundancy bits and its chip. The non-binary capacitor array with redundancy bits comprises a common-mode voltage, analog signal input, no less than one redundancy bit capacitor and multiple capacitors; each capacitor of capacitors with redundancy bits and multiple capacitors is connected in parallel between common-mode voltage and analog signal input and marked in a sequence from highest to lowest/lowest to highest bit; the sum of the capacitance of capacitors from the lowest bit capacitor to an random capacitor must be no less than the capacitance of the higher bit capacitor adjacent to the random capacitor. The ratio of the capacitance of each capacitor to the capacitance of unit capacitor is set to be positive. The capacitor array is applied into an analog-to-digital converter or fabricated as a chip.

Embodiments of the present invention provide a digital-to-analog conversion circuit, where the digital-to-analog conversion circuit includes a signal amplitude detector and a digital-to-analog converter. When the signal amplitude detector detects a low signal amplitude, a first current module in the digital-to-analog converter operates normally and a second current module in the digital-to-analog converter stops operating. In addition, when stopping operating, the second current module is in a state of a third bias voltage and a fourth bias voltage that are generated by a second bias circuit. When the amplitude detector detects a high signal amplitude subsequently, the second current module resumes normal operation. After operating normally, the second current module switches back to a first bias voltage and a second bias voltage that are generated by a first bias circuit. This reduces a nonlinearity problem caused before a second current module resumes normal operation.

Devices and methods for digital to analogue conversion (DAC) are provided, in which the analogue outputs of an even number of digital to analogue converters are combined. The individual converters operate on the same data but there is a relative time delay between the input digital signal received by one or more of the converters and the input digital signal received by other of the converters, wherein the delay is a fraction of the data sample period. Moreover, the data signal fed to half of the converters has an inverse relationship with the data signal fed to the other half of the converters and their analogue outputs are subtracted. Dither and filtering techniques may also be employed.

A first analog block includes a first plurality of switched capacitors and a second analog block includes a second plurality of switched capacitors. A switch associated with the first plurality of switched capacitors as well as a switch associated with the second plurality of switched capacitors may be configured based on one or more analog functions. The configuring of the first analog and the second analog block may include the configuring of the switch associated with the first plurality of switched capacitors when the analog function is associated with a first single ended signal and the configuring of both the switch associated with the first plurality of switched capacitors and the switch associated with the second plurality of switched capacitors when the analog function is associated with a differential signal.

Semiconductor devices and methods are provided. A semiconductor device according to the present disclosure includes a substrate having a first area and a second area, a plurality of fin structures extending along a direction over the first area and the second area of the substrate, a first transistor and a second transistor in the first area, a first isolation structure disposed between the first transistor and the second transistor, a first isolation structure disposed between the first transistor and the second transistor, a third transistor and a fourth transistor in the second area, and a second isolation structure disposed between the third transistor and the fourth transistor. The first isolation structure includes a first width along the direction and the second isolation structure includes a second width along the direction. The second width is greater than the first width.

An analog-to-digital converter of non-binary capacitor array with redundancy bits and its chip. The non-binary capacitor array with redundancy bits comprises a common-mode voltage, analog signal input, no less than one redundancy bit capacitor and multiple capacitors; each capacitor of capacitors with redundancy bits and multiple capacitors is connected in parallel between common-mode voltage and analog signal input and marked in a sequence from highest to lowest/lowest to highest bit; the sum of the capacitance of capacitors from the lowest bit capacitor to an random capacitor must be no less than the capacitance of the higher bit capacitor adjacent to the random capacitor. The ratio of the capacitance of each capacitor to the capacitance of unit capacitor is set to be positive. The capacitor array is applied into an analog-to-digital converter or fabricated as a chip.

Disclosed is an input impedance boosting apparatus. More particularly, an input impedance boosting apparatus including an analog-to-digital converter; an input capacitor connected to an input terminal of the analog-to-digital converter and a ground line and including a first shielding metal formed thereunder; a feedback capacitor connected onto a positive feedback loop of the analog-to-digital converter and including a second shielding metal formed thereunder; and an impedance booster connected to both ends of the feedback capacitor and configured to boost an input impedance based on a first parasitic component formed between the input capacitor and the first shielding metal and a second parasitic component formed between the feedback capacitor and the second shielding metal is provided.

Semiconductor devices and methods are provided. A semiconductor device according to the present disclosure includes a substrate having a first area and a second area, a plurality of fin structures extending along a direction over the first area and the second area of the substrate, a first transistor and a second transistor in the first area, a first isolation structure disposed between the first transistor and the second transistor, a first isolation structure disposed between the first transistor and the second transistor, a third transistor and a fourth transistor in the second area, and a second isolation structure disposed between the third transistor and the fourth transistor. The first isolation structure includes a first width along the direction and the second isolation structure includes a second width along the direction. The second width is greater than the first width.