The disclosure relates to an error-compensated direct digital modulation device, including: a direct digital radio frequency modulator (DDRM), configured to generate a radio frequency (RF) signal based on a modulation of a digital baseband signal; an error estimator configured to determine an error signal resulting from a deviation based on the generated RF signal and a representation of the digital baseband signal; and an error compensator configured to subtract the error signal from the RF signal to provide an error compensated RF signal.

A method of DAC mismatch calibration in a SAR ADC is disclosed. In one aspect, the method comprises determining a number of bits of an analog input signal (V.sub.IN), detecting if a binary code determined from the analog input signal (V.sub.IN) matches at least one trigger code, using at least one setting code to determine a calibration residue signal (V*.sub.RES) and a calibration bit (B*.sub.LSB), analyzing a least significant bit of the digital signal (C.sub.OUT) and the calibration bit (B*.sub.LSB), determining an indication of a presence of DAC mismatch, and calibrating the DAC mismatch. As the determination of the calibration bit (B*.sub.LSB) requires only one additional comparison, when compared to the normal operation, the normal operation does not need to be interrupted. Therefore, the calibration can be done in the background and, as such, can be performed frequently thereby taking into account time-varying changes due to environmental effects.

The present disclosure provides an analog readout preprocessing circuit for a CMOS image sensor and a control method thereof. The analog readout preprocessing circuit comprises an extended count-type integration cycle-successive approximation hybrid analog-to-digital conversion capacitor network 1 configured to achieve readout and analog-to-digital conversion of signals output from the CMOS image sensor; an operational amplifier configured to utilize virtual short of two input terminals of the operational amplifier and the charge conservation principle, to achieve a function of extended count-type integration cycle-successive approximation hybrid analog-to-digital conversion, where the extended count-type integration can effectively reduce a thermal noise and a flicker noise within the image sensor; a comparator configured to compare voltages at two terminals to achieve a function of quantization of signals; and a control signal generator configured to provide control signals.

A programmable temperature compensated voltage reference is disclosed. In an exemplary embodiment, an apparatus includes a digital-to-analog converter (DAC) that uses a reference voltage and a code to generate a DAC output voltage. The apparatus also includes a temperature compensator that uses a temperature measurement (T) and the DAC code to generate a temperature compensation signal. The temperature compensation signal is represented by a third order polynomial equation. The apparatus also includes a signal combiner that combines the DAC output voltage and the temperature compensation signal to generate a temperature compensated programmable reference voltage.

The disclosure relates to a circuit for stabilizing a digital-to-analog converter reference voltage. One example embodiment is a circuit for stabilizing a voltage on a reference node. The circuit includes a digital-to-analog converter that includes an array of capacitors and arranged for: receiving an input voltage via an input node, receiving a voltage via a reference node and a digital-to-analog code via a controller node, and outputting a digital-to-analog output voltage. The circuit also includes a capacitive network on the reference node comprising a fixed capacitor arranged to be pre-charged to an external reference voltage and a variable capacitor arranged to be pre-charged to an external auxiliary voltage. Further, the circuit includes a measurement block. In addition, the circuit includes a calibration block arranged for determining an updated setting of the variable capacitor based on the digital-to-analog code and the measured voltage on the reference node.

The disclosure relates to a circuit for stabilizing a digital-to-analog converter reference voltage. One example embodiment is a circuit for stabilizing a voltage on a reference node. The circuit includes a digital-to-analog converter that includes an array of capacitors and arranged for: receiving an input voltage via an input node, receiving a voltage via a reference node and a digital-to-analog code via a controller node, and outputting a digital-to-analog output voltage. The circuit also includes a capacitive network on the reference node comprising a fixed capacitor arranged to be pre-charged to an external reference voltage and a variable capacitor arranged to be pre-charged to an external auxiliary voltage. Further, the circuit includes a measurement block. In addition, the circuit includes a calibration block arranged for determining an updated setting of the variable capacitor based on the digital-to-analog code and the measured voltage on the reference node.

A programmable temperature compensated voltage reference is disclosed. In an exemplary embodiment, an apparatus includes a digital-to-analog converter (DAC) that uses a reference voltage and a code to generate a DAC output voltage. The apparatus also includes a temperature compensator that uses a temperature measurement (T) and the DAC code to generate a temperature compensation signal. The temperature compensation signal is represented by a third order polynomial equation. The apparatus also includes a signal combiner that combines the DAC output voltage and the temperature compensation signal to generate a temperature compensated programmable reference voltage.

Methods and apparatus for wireless communication using a transmitter capable of digital predistortion (DPD) and having a main signal path separated from a predistortion signal path, each path including a digital-to-analog converter (DAC). An example apparatus generally includes a main signal path comprising a first DAC, a power amplifier, and a combiner, the combiner being disposed in the main signal path between an output of the first DAC and an input of the power amplifier. The apparatus also includes a predistortion signal path comprising a second DAC, wherein the combiner is configured to combine a predistortion signal in the predistortion signal path with a main signal in the main signal path.

An analog-to-digital converter (ADC) includes bit trial circuitry configured to perform ADC bit trials that compare an input signal to states of weighted circuit elements, a dither digital-to-analog converter (DAC) to receive a dither sequence and apply a dither signal to the bit trial circuitry, and calibration circuitry. The calibration circuitry is configured to input a dither sequence into the ADC bit trials as dithered bit trials; determine an effect of the dither sequence on results of the dithered bit trials; and update correction factors used to adjust results of the ADC bit trials using the determined effect of the dither sequence.

A delay-domain analog-to-digital converter (ADC) including first and second ADCs and corresponding look-up table (LUT) memories. Control logic controls the first ADC to convert a first analog level plus a first offset to a first digital value; controls the second ADC to convert the first analog level plus a second offset to a second digital value; and computes a first difference value between the first and second digital values. The control logic further controls the first ADC to convert the first analog level minus the first offset to a third digital value; controls the second ADC to convert the first analog level plus the second offset to a fourth digital value; computes a second difference value between the third and fourth digital values; and adjusts a correction value for the first analog level in the LUT memory based on a third difference between the first and second difference values.