H03M1/127

Non-uniform sampling implementation

This application discloses an implementation of a novel non-uniform sampling technique for a burst type signal. A simple circuit is developed that implements an analog computation of a complex digital calculation to skip the unnecessary samples and choose the optimum next sample. Then the optimum samples are selected for further processing which results in overall cost and power consumption reduction.

Digital signal processing of randomly jittered under-sampled sequence
12113553 · 2024-10-08 · ·

Methods/systems employ randomly jittered under-sampling to reduce a sampling rate required to convert an analog signal to a digital signal in electronic devices and other applications that perform digital signal processing on the signal. The methods/systems can greatly reduce the nominal sampling rate for such applications where RMS, peak and mean estimates of the signal are desired for both the entire band-limited signal and separate estimates for each frequency component. This can in turn result in large cost savings, as less complex and thus less expensive controllers and related components may be used to perform the sampling. As well, the methods/systems herein can provide reasonably accurate waveform estimates that allow additional cost savings in bill of materials (BOM) and printed circuit board assembly (PCBA) footprint and real-estate by eliminating the need for certain analog components, such as signal conditioning components.

Analog to digital converting device and operating method thereof

An analog-to-digital converting device configured to convert an analog signal into a digital signal, including a meta-stability detection unit configured to output a meta-stability signal based on a comparison result, wherein the comparison result is determined by comparing a comparison voltage of each bit of the digital signal with the analog signal; a counter configured to count a number of times that the comparison voltage of each bit of the digital signal is compared with the analog signal; and a control logic configured to detect a bit at which meta-stability has occurred from among bits of the digital signal based on the meta-stability signal and the counted number.

WAVEFORM-CODING FOR MULTICARRIER WAKE UP RADIO FRAME
20180227070 · 2018-08-09 ·

Waveform-coding is applied to map successive on-off-keying (OOK) data bits onto successive multicarrier modulated symbols in time domain, wherein each multicarrier modulated symbol includes a set of sub-carriers in which alternating sub-carriers are set to ones and zeros in frequency domain. The waveform coded multicarrier modulated symbols are up-converted to a carrier frequency to provide a data signal that is transmitted over a wireless channel.

Randomly jittered under-sampling for efficient data acquisition and analysis in digital metering, GFCI, AFCI, and digital signal processing applications
12143128 · 2024-11-12 · ·

Methods/systems employ randomly jittered under-sampling to reduce a sampling rate required to estimate the amplitude of high-frequency signals in circuit breakers, power meters, and other digital signal processing applications. The methods/systems can greatly reduce the nominal sampling rate for applications where RMS, peak and mean estimates of the signal are desired for both the entire band-limited signal and separate estimates for each frequency component. This can in turn result in large cost savings, as less complex and thus less expensive controllers and related components may be used to perform the sampling. As well, the methods/systems herein can provide reasonably accurate waveform estimates that allow additional cost savings in bill of materials (BOM) and printed circuit board assembly (PCBA) footprint and real-estate by eliminating the need for certain analog components, such as signal conditioning components.

Randomly jittered under-sampling and phase sampling for time-frequency and frequency analyses in AFCI, GFCI, metering, and load recognition and disaggregation applications
12273129 · 2025-04-08 · ·

Methods/systems employ randomly jittered under-sampling to reduce a sampling rate required to estimate the amplitude of high-frequency signals in circuit breakers, power meters, and other digital signal processing applications. The methods/systems can greatly reduce the nominal sampling rate for applications where RMS, peak and mean estimates of the signal are desired for both the entire band-limited signal and separate estimates for each frequency component. This can in turn result in large cost savings, as less complex and thus less expensive controllers and related components may be used to perform the sampling. As well, the methods/systems herein can provide reasonably accurate waveform estimates that allow additional cost savings in bill of materials (BOM) and printed circuit board assembly (PCBA) footprint and real-estate by eliminating the need for certain analog components, such as signal conditioning components.

ADAPTIVE ANALOG-TO-DIGITAL CONTROLLER
20250274130 · 2025-08-28 ·

Various embodiments disclosed herein relate to adaptive clock signal management, and more specifically, to transitioning between clock frequencies to convert analog signals to digital signals at dynamic sampling rates. In an example embodiment, a device including an analog-to-digital converter (ADC) and a control circuit coupled to the ADC is provided. The ADC is configured to receive a first analog signal, receive a first clock signal, and generate a first set of digital values corresponding to the first analog signal based on the first clock signal. The control circuit is configured to determine that a change in the first set of digital values satisfies a first threshold value and increase the first clock signal from a first frequency to a second frequency in response to determining that the change in the first set of digital values satisfies the first threshold value.

AD conversion device

An AD conversion device includes an AD converter that outputs an analog signal as sampling data for every sampling point based on a sampling frequency, a controller, and a storage circuit, the controller includes a buffer memory which temporarily stores the sampling data from the AD converter in time series and from which the sampling data is read out in time series, and a decimation controller, the decimation controller outputs a write-enable signal indicating write-enabled for the selected sampling data in the decimation region and the sampling data in the high-speed sampling region, and outputs decimation bit information indicating whether the sampling data is the sampling data of the decimation region or the sampling data of the high-speed sampling region, and the storage circuit stores the sampling data stored in the buffer memory in association with the decimation bit information, in response to the write-enable signal.