Techniques to reduce the on-time of a multi-stage ADC circuit by combining the settling time of a signal conditioning circuit, e.g., buffer circuit, and the setting time of a residue amplifier when cancelling the offset of the signal conditioning circuit. The techniques can allow the signal conditioning circuit and the residue amplifier to settle together.

VCO ADCs consume relatively little power and require less area than other ADC architectures. However, when a VCO ADC is implemented by itself, the VCO ADC can have limited bandwidth and performance. To address these issues, the VCO ADC is implemented as a back end stage in a VCO-based continuous-time (CT) pipelined ADC, where the VCO-based CT pipelined ADC has a CT residue generation front end. Optionally, the VCO ADC back end has phase interpolation to improve its bandwidth. The pipelined architecture dramatically improves the performance of the VCO ADC back end, and the overall VCO-based CT pipelined ADC is simpler than a traditional continuous-time pipelined ADC.

There is provided a successive-approximation type AD converter and a pipeline type AD converter without delay due to sample hold. A successive-approximation type AD converter 1 includes: receiving circuits configured to output the analog input signal according to the received analog input signal; subtractors configured to calculate subtraction signals between the analog input signal in each of n successive conversions and comparison signals obtained by DA-converting the control values by DA converters; comparators configured to determine a high-low relationship between the voltages of the subtraction signals and the reference voltage; a control circuit configured to update the control values so that the comparison signals approach the analog input signal based on the comparison results; and an output register configured to output the digital output signal based on the comparison results of the comparators.

There is provided a successive-approximation type AD converter and a pipeline type AD converter without delay due to sample hold. A successive-approximation type AD converter 1 includes: receiving circuits configured to output the analog input signal according to the received analog input signal; subtractors configured to calculate subtraction signals between the analog input signal in each of n successive conversions and comparison signals obtained by DA-converting the control values by DA converters; comparators configured to determine a high-low relationship between the voltages of the subtraction signals and the reference voltage; a control circuit configured to update the control values so that the comparison signals approach the analog input signal based on the comparison results; and an output register configured to output the digital output signal based on the comparison results of the comparators.

Multiplying digital-to-analog converter (MDACs) are implemented in pipelined ADCs to generate an analog output being fed to a subsequent stage. A switched capacitor MDAC can be implemented by integrating a capacitor digital-to-analog converter (DAC) with charge pump gain circuitry. The capacitor DAC can implement the DAC functionality while the charge pump gain circuitry can implement subtraction and amplification. The resulting switched capacitor MDAC can leverage strengths of nanometer process technologies, i.e., very good switches and highly linear capacitors, to achieve practical pipelined ADCs. Moreover, the switched capacitor MDAC has many benefits over other approaches for implementing the MDAC.

A switched-capacitor gain stage circuit and method include an amplifier connected to an input sampling circuit with sampling switched capacitors for coupling an input voltage and a first or second reference voltage to one or more central nodes during a sampling phase and for coupling the one or more central nodes to an amplifier input during a gain phase, wherein a reference loading circuit uses a plurality of sampling switched capacitors connected in a switching configuration to selectively couple a first reference voltage and/or a second reference voltage to the central node by pre-charging the plurality of sampling switched capacitors with the first and second reference voltages during the sampling phase, and by coupling each of the first and second reference voltages to at least one of the plurality of sampling switched capacitors when connected to the central node during the gain phase.

An analog-to-digital converter (ADC) and a method are disclosed. The ADC has a quantizer. The quantizer comprises a linear-feedback shift register (LFSR), a decoder configured to provide a plurality of switch control signals at a plurality of decoder outputs, respectively, the plurality of switch control signals responsive to a LFSR value of the LFSR output; an electrical reference, the electrical reference having a plurality of reference outputs, the electrical reference configured to provide a plurality of reference levels at the plurality of reference outputs, respectively; a first switch providing a first switch output and a second switch output; and a comparator, the comparator having a signal input, a first reference input, and a second reference input, the first reference input connected to the first switch output, and the second reference input connected to the second switch output.

A pipelined analog-to-digital converter has an analog signal input. A first input sample-and-hold circuit is connected to the analog signal input. An amplifier is connected to an output of the first input sample-and-hold circuit. A second input sample-and-hold circuit has an input connected to the analog signal input in parallel to the first input sample-and-hold circuit. An AD/DA conversion path is connected to an output of the second input sample-and-hold circuit. A first output sample-and-hold circuit has an input connected to an output of the amplifier. A second output sample-and-hold circuit has an input connected to the output of the amplifier. The amplifier, the first output sample-and-hold circuit, the second input sample-and-hold circuit, and the AD/DA conversion path are part of a converter stage and outputs of the converter stage are inputs to a following converter stage.

Multi-step ADCs performs multi-step conversion by generating a residue for a subsequent stage to digitize. To generate a residue, a stage in the multi-step ADC would reconstruct the input signal to the stage using a feedforward digital to analog converter (DAC). Non-linearities in the DAC can directly affect the overall performance of the multi-step ADC. To reduce power consumption and complexity of analog circuit design, digital background calibration schemes are implemented to address the non-linearities. The non-linearities that the calibration schemes address can include reference, DAC, and quantization non-linearities.

A pipelined analog-to-digital converter (ADC) using a multiplying digital-to-analog converter (MDAC) and two sub-range analog-to-digital converters (sub-range ADCs) is disclosed. The MDAC samples an analog input and performs multiplication on the sampled analog input based on control bits. The first sub-range ADC provides the MDAC with the control bits. The second sub-range ADC is coupled to the MDAC for conversion of a multiplied signal output from the MDAC. The first sub-range ADC samples the analog input to generate the control bits for the MDAC as well as pre-estimated bits for the second sub-range ADC. The second sub-range ADC operates based on the pre-estimated bits and thereby a first section of digital bits are generated by the second sub-range ADC. A second section of digital bits are provided by the first sub-range ADC. The first and second sections of digital bits represent the analog input.