Herein disclosed are multiple embodiments of a signal-processing circuit that may be utilized in various circuits, including conversion circuitry. The signal-processing circuit may receive an input and produce charges on multiple different capacitors during different phases of operation based on the input. The charges stored on two or more of the multiple different capacitors may be utilized for producing an output of the signal-processing circuit, such as by combing the charges stored on two or more of the multiple different capacitors. Utilizing the charges on the multiple different capacitors may provide for a high level of accuracy and robustness to variations of environmental factors, and/or a low noise level and power consumption when producing the output.

Multi-step ADCs performs multi-step conversion by generating a residue for a subsequent stage to digitize. To generate a residue, a stage in the multi-step ADC would reconstruct the input signal to the stage using a feedforward digital to analog converter (DAC). Non-linearities in the DAC can directly affect the overall performance of the multi-step ADC. To reduce power consumption and complexity of analog circuit design, digital background calibration schemes are implemented to address the non-linearities. The non-linearities that the calibration schemes address can include reference, DAC, and quantization non-linearities.

Herein disclosed are multiple embodiments of a signal-processing circuit that may be utilized in various circuits, including conversion circuitry. The signal-processing circuit may receive an input and produce charges on multiple different capacitors during different phases of operation based on the input. The charges stored on two or more of the multiple different capacitors may be utilized for producing an output of the signal-processing circuit, such as by combing the charges stored on two or more of the multiple different capacitors. Utilizing the charges on the multiple different capacitors may provide for a high level of accuracy and robustness to variations of environmental factors, and/or a low noise level and power consumption when producing the output.

An analog to digital converter (ADC) circuit includes a first stage for converting a first analog voltage signal to a first digital signal including a first portion of a digital output signal representing the first analog voltage signal, and generate a first residue voltage based on the first analog voltage signal and the first digital signal. A first amplifier control unit generates a first amplifier start signal based on a second stage ready signal indicating that a second stage is ready to process a second analog voltage signal. In response to the second stage ready signal, a first amplifier generates the second analog voltage signal based on the first residue voltage. The second stage is configured to generate the second stage ready signal, receive the second analog voltage signal, and convert the second analog voltage signal to a second digital signal including a second portion of the digital output signal.

A pipelined analog-to-digital converter (ADC) and an operating method are provided. The pipelined ADC includes a multiplying digital-to-analog converter (MDAC) and a sub-ADC. The MDAC alternatively operates in an amplifying phase and a sampling phase according to two non-overlapping clocks, and performs operations on an input signal in the amplifying phase according to a target voltage determined by a digital code. The sub ADC includes multiple comparators, a determination circuit, and an encoding circuit. The comparators generate multiple comparison results by comparing the input signal with multiple predetermined voltages. The determination circuit generates multiple comparison completion signals in a non-overlapping interval of the two clocks according to the comparison results. The comparison completion signals respectively indicate whether the comparators complete the comparison. The encoding circuit determines the digital code according to the comparison results and the comparison completion signals.

A frontend circuit of a time-interleaved ADC is provided. The frontend circuit can include a track-and-hold circuit to sample an analog input signal to the ADC, a sub-ADC circuit to convert the sampled analog input signal to a digital output signal, and a source-follower circuit. An input of the source-follower circuit can be coupled to an output of the track-and-hold circuit, and an output of the source-follower circuit can be coupled to an input of the sub-ADC circuit. The source-follower circuit is to provide buffering between the track-and-hold circuit and the sub-ADC circuit. The circuit further includes a common-mode-adjusting circuit to dynamically adjust common-mode settings of the time-interleaved ADC. While adjusting the common-mode settings, the common-mode-adjusting circuit can adjust, separately, an input common-mode voltage of the track-and-hold circuit and an input common-mode voltage of the sub-ADC circuit based on current Process, Voltage, and Temperature (PVT) conditions.

A pipelined analog-to-digital converter (ADC) and an operating method are provided. The pipelined ADC includes a multiplying digital-to-analog converter (MDAC) and a sub-ADC. The MDAC alternatively operates in an amplifying phase and a sampling phase according to two non-overlapping clocks, and performs operations on an input signal in the amplifying phase according to a target voltage determined by a digital code. The sub-ADC includes multiple comparators, a determination circuit, and an encoding circuit. The comparators generate multiple comparison results by comparing the input signal with multiple predetermined voltages. The determination circuit generates multiple comparison completion signals in a non-overlapping interval of the two clocks according to the comparison results. The comparison completion signals respectively indicate whether the comparators complete the comparison. The encoding circuit determines the digital code according to the comparison results and the comparison completion signals.

A digital correction method for dynamic range expansion of multiple ADCs includes: obtaining gain and offset correction values of other channels relative to a standard channel CH.sub.1 based on iterative computations through positive and negative amplitude auxiliary values and positive and negative base values, then performing gain-offset error correction on the other channels, and then calculating phase differences of the other channels relative to the standard channel CH.sub.1 and constructing fractional delay filters with a Farrow structure corresponding to the channels, correcting sampling data X.sub.2, . . . , X.sub.M after performing the gain-offset error correction. Digital correction of sampling data collected from multiple channels in a multi-ADC system is realized while ensuring that respective dynamic ranges of the sampling data with different gains output by the multiple channels are not lost.

A communication unit receiver comprising: a multi-section analog to digital converter, ADC, configured to receive an analog signal and convert at least a first portion of the analog signal into a digital signal using a first ADC dynamic range. A modem, coupled to the multi-section ADC, is configured to: process the digital signal; determine a signal-to-noise ratio, SNR, for sub-carriers of the analog signal; and output an ADC selection signal to the multi-section ADC that selects a subset of sections of the multi-section ADC, where the selection signal is based at least partly on the determined SNR. Only the subset of sections of the multi-section analog to digital converter, ADC is configured to convert a second portion of the analog signal into a digital signal using a second ADC dynamic range that is less than the first dynamic range.

A slope analog-to-digital converter, ADC, comprises: an input unit comprising a sampling capacitor, wherein the input unit is configured to during an initial period obtain a sampled value of an analog input signal and, during a conversion period, hold the sampled value across the sampling capacitor; and a comparator configured to determine a most significant bit of the analog input signal during the initial period; wherein the ADC during the conversion period is configured to receive a slope signal and to be adapted based on the determined most significant bit such that the comparator is further configured to adaptively compare the sampled value and the slope signal for converting the sampled value to a digital representation.