A method for calibrating analog-to-digital conversion includes converting, by an analog-to-digital converter (ADC), a first input voltage to a first digital code. The first input voltage is generated from a reference voltage used as a reference voltage by the ADC. The method includes converting, by the ADC, a second input voltage to a second digital code. The second input voltage is generated from the reference voltage used as the reference voltage by the ADC. The method also includes calculating a calibration factor based on the first digital code, the second digital code, the first input voltage, and the second input voltage, converting, by the ADC, a third voltage to a third digital code, and correcting the third digital code using the calibration factor.

For analog-to-digital converters (ADCs) which utilize a feedback digital-to-analog converter (DAC) for conversion, the final analog output can be affected or distorted by errors of the feedback DAC. A digital measurement technique can be implemented to determine switching mismatch error for the feedback DAC in a continuous-time delta-sigma modulator (CTDSM) or in a continuous-time pipeline modulator. The methodology forces each DAC unit elements (UEs) to switch a certain amount times and then use the modulator itself to measure the errors caused by those switching activities respectively. The obtained errors can be stored in a look-up table and fully corrected in digital domain or analog domain.

For analog-to-digital converters (ADCs) which utilize a feedback digital-to-analog converter (DAC) for conversion, the final analog output can be affected or distorted by errors of the feedback DAC. A digital measurement technique can be implemented to determine switching mismatch error for the feedback DAC in a continuous-time delta-sigma modulator (CTDSM) or in a continuous-time pipeline modulator. The methodology forces each DAC unit elements (UEs) to switch a certain amount times and then use the modulator itself to measure the errors caused by those switching activities respectively. The obtained errors can be stored in a look-up table and fully corrected in digital domain or analog domain.

Continuous time pipeline, level-crossing (LC), analog-to-digital converters (ADCs) use a plurality of stages from a first stage to a last stage. Each stage has an array of comparators that are provided with an array of reference voltage levels. Each stage is configured to detect level crossings of increasing fineness compared to the preceding stage such that the accuracy of a digitized representation of an input signal can be increased by adding stages as well as increasing the number of comparators in each stage. The voltage error in the digitized representation of the signal that remains after each stage provides the input to the subsequent stage. The continuous time pipeline LC ADCs are also applied to analog signal processing and software defined radios.

In an example, a system includes a pipelined analog-to-digital converter (ADC) having a main path and an auxiliary path. The main path includes a first stage having a sampling switch, a flash ADC having an input coupled to the sampling switch, a digital-to-analog converter (DAC) having an input coupled to an output of the flash ADC, and a first amplifier having an input coupled to an output of the DAC and the sampling switch. The main path includes a second stage coupled to the first stage and an input of a second amplifier. The main path also includes a backend ADC having an input coupled to an output of the second amplifier. The auxiliary path includes a plurality of metastability comparators coupled to the flash ADC.

A digital correction method for dynamic range expansion of multiple ADCs includes: obtaining gain and offset correction values of other channels relative to a standard channel CH.sub.1 based on iterative computations through positive and negative amplitude auxiliary values and positive and negative base values, then performing gain-offset error correction on the other channels, and then calculating phase differences of the other channels relative to the standard channel CH.sub.1 and constructing fractional delay filters with a Farrow structure corresponding to the channels, correcting sampling data X.sub.2, . . . , X.sub.M after performing the gain-offset error correction. Digital correction of sampling data collected from multiple channels in a multi-ADC system is realized while ensuring that respective dynamic ranges of the sampling data with different gains output by the multiple channels are not lost.

An example apparatus includes: combination circuitry having a first input, a second input, and an output; analog-to-digital converter (ADC) circuitry having an input and an output, the input of the ADC circuitry coupled to the output of the combination circuitry; digital-to-analog converter (DAC) circuitry having an input and an output, the input of the DAC coupled to the output of the ADC circuitry; a resistor having a first terminal and a second terminal, the first terminal of the resistor coupled to the first input of the combination circuitry; amplifier circuitry having an input coupled to the output of the DAC circuitry and the second terminal of the resistor.