Disclosed are a two-stage audio gain circuit based on analog-to-digital conversion and an audio terminal. The two-stage audio gain circuit includes a PGA configured to receive an analog audio signal and perform programmable gain amplification processing on the received analog audio signal; an ADC configured to convert the analog audio signal after the programmable gain amplification processing into a digital audio signal and output the digital audio signal; a first AGC gain unit configured to perform a first AGC processing on the digital audio signal and output a first gain adjustment value to the PGA, for the PGA to perform gain adjustment on the received analog audio signal; and a second AGC gain unit configured to perform a second AGC processing on the digital audio signal and output a second gain adjustment value to the PGA, for the PGA to perform gain adjustment on the received analog audio signal.

The present invention relates to a device and a method for measurement of electrical signals in an industrial automation and control system. The device comprises an input circuit, configured to receive an electrical input signal (100), scale the electrical input signal by a scaling factor and to set the scaling factor according to a scaling signal (110), an Analog-to-Digital Converter, ADC (220), which is electrically connected to the input circuit, wherein the ADC is configured to convert the scaled electrical input signal (103) into an intermediate digital signal (120), and a first signal path (211), connected to an digital end of the ADC, configured to create the scaling signal (110) and to send the scaling signal (110) to the input circuit, wherein, based on the intermediate digital signal of a sample period and the scaling factor of the sample period, the scaling factor for a subsequent sample period is set.

Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a receiver device may identify an analog to digital converter (ADC) clipping rate for one or more measurement windows. The receiver device may modify, based at least in part on a determination that the ADC clipping rate does not satisfy a threshold, a low noise amplifier (LNA) gain value to be used by the receiver device. The receiver device may receive a signal using the modified LNA gain value. Numerous other aspects are provided.

A Wi-Fi wake-up receiver that receives wake-up signals encoded using orthogonal frequency division multiplexing based on-off keying (OFDM-OOK) modulation includes receiver circuitry having analog envelope detector circuitry configured to non-linearly down-convert an input signal and provide an energy signal for sampling by an analog-to-digital converter (ADC). A wake-up signal for waking up a main radio in a Wi-Fi device can be based on the digitized energy signal. The receiver circuitry can further include, upstream of the envelope detector circuitry and the ADC in the signal chain, an analog mixer for linearly down-converting the input signal and a low-pass filter for attenuating adjacent-channel interferer (ACI) signals prior to the non-linear down-conversion by the envelope detector circuitry. Sampling of the energy signal rather than the higher-bandwidth input signal yield power savings in the ADC and associated circuitry such as a modem.

A unity-gain buffer circuit structure, used to receive an input voltage and output an output voltage, includes a first operational amplifier and a second operational amplifier. The first operational amplifier includes a first positive input, a first output and a first negative input. The second operational amplifier, coupled electrically with the first operational amplifier, includes a second positive input, a second output and a second negative input. The second positive input is used to receive the output voltage. The second output, coupled with first negative input, is used to output a second output voltage. The second negative input, coupled with the second output, is used to receive the second output voltage. After the first negative input receives the second output voltage, an offset voltage between the output voltage outputted from the first operational amplifier and the input voltage received by the first operational amplifier is close to 0.

A method for measuring power of a received signal includes the following steps: determining N type(s) of sampling rate(s) of an analog-to-digital converter (ADC) according to a theoretical minimum sampling rate of the received signal; using the ADC to sample the received signal according to the N type(s) of sampling rate(s) within a period of sampling time and thereby obtaining sampling results; and measuring the power of the received signal according to the sampling results and the period of sampling time, wherein the theoretical minimum sampling rate is corresponding to a signal cycle of the received signal, the N is a positive integer, the N type(s) of sampling rate(s) is/are corresponding to N type(s) of sampling cycle(s), and any of the N type(s) of sampling cycle(s) and the signal cycle are coprime.

A unity-gain buffer circuit structure, used to receive an input voltage and output an output voltage, includes a first operational amplifier and a second operational amplifier. The first operational amplifier includes a first positive input, a first output and a first negative input. The second operational amplifier, coupled electrically with the first operational amplifier, includes a second positive input, a second output and a second negative input. The second positive input is used to receive the output voltage. The second output, coupled with first negative input, is used to output a second output voltage. The second negative input, coupled with the second output, is used to receive the second output voltage. After the first negative input receives the second output voltage, an offset voltage between the output voltage outputted from the first operational amplifier and the input voltage received by the first operational amplifier is close to 0.

Certain aspects are directed to an apparatus configured for wireless communication. The apparatus may include a memory comprising instructions, and one or more processors configured to execute the instructions. In some examples, the one or more processors are configured to cause the apparatus to obtain a sample of an analog signal. In some examples, the one or more processors are configured to cause the apparatus to output the sample to an analog-to-digital converter (ADC) via one of at least a first path or a second path based at least in part on whether the sample satisfies a first threshold condition or a second threshold condition.

An electricity usage monitor may include a coupling component to couple the electricity usage monitor to monitor an electrical circuit, a meter to measure electricity usage of the electrical circuit, an encoder to receive, from the meter, an electricity usage measurement to generate a measurement transmission based on the electricity usage measurement, and a communication interface configured to receive the measurement transmission from the encoder and to transmit the measurement transmission into a communication network for communication to a destination on the communication network.

A circuit includes a switched capacitor circuit and a voltage generator circuit. The switched capacitor circuit includes first, second, third, and fourth switches and first and second capacitors. The first capacitor has first and second terminals, the first terminal coupled to the first switch. The second capacitor has first and second terminals, the second terminal coupled to the second switch. The third switch has a terminal coupled to the second terminals of the first and second capacitors. The fourth switch has first and second terminals, the first terminal coupled the terminal of the third switch and to the second terminals of the first and second capacitors. The voltage generator circuit has an output coupled to the second terminal of the fourth switch and is configured to provide a common mode output bias voltage at the second terminal of the fourth switch responsive to a common mode input bias voltage.