An encoder system includes a configurable detector array, wherein the configurable detector array includes a plurality of detectors. The encoder system may also include a memory operable to store a partition map that defines a state for each of the plurality of detectors. The encoder system may also include an emitter operable to generate a flux modulated by a motion object, wherein the configurable detector array is operable to receive the flux and generate respective current outputs for each of the detectors in response to the flux. In an embodiment, the current outputs from detectors having a same state are grouped together. The encoder system may also include one or more current duplicators to duplicate the current outputs from detectors having one state to group with the current outputs from detectors having a different state. The encoder system may also adjust weights of the current outputs.

An encoder system includes a configurable detector array, wherein the configurable detector array includes a plurality of detectors. The encoder system may also include a memory operable to store a partition map that defines a state for each of the plurality of detectors. The encoder system may also include an emitter operable to generate a flux modulated by a motion object, wherein the configurable detector array is operable to receive the flux and generate respective current outputs for each of the detectors in response to the flux. In an embodiment, the current outputs from detectors having a same state are grouped together. The encoder system may also include one or more current duplicators to duplicate the current outputs from detectors having one state to group with the current outputs from detectors having a different state. The encoder system may also adjust weights of the current outputs.

An apparatus includes a processor, a Phase-Locked Loop Waveform Generator (PLLWG), a Voltage Controlled Oscillator (VCO), a demodulator, signal conditioning circuitry, and an Analog-to-Digital Converter (ADC). The processor generates control command signals, receives a digital data input signal, and performs spectrum analysis on the digital data input signal. The PLLWG is coupled to the processor, receives the control command signals, and generates a charge pump output signal based on the control command signals. The VCO is coupled to the PLLWG, receives a tuning signal based on the charge pump output signal, and outputs a VCO output signal based on the tuning signal. The demodulator receives an incoming modulated signal and the VCO output signal, and outputs an analog output signal based on the incoming modulated signal and the VCO output signal. The ADC converts the analog output signal into the digital data input signal.

An apparatus includes a processor, a Phase-Locked Loop Waveform Generator (PLLWG), a Voltage Controlled Oscillator (VCO), a demodulator, signal conditioning circuitry, and an Analog-to-Digital Converter (ADC). The processor generates control command signals, receives a digital data input signal, and performs spectrum analysis on the digital data input signal. The PLLWG is coupled to the processor, receives the control command signals, and generates a charge pump output signal based on the control command signals. The VCO is coupled to the PLLWG, receives a tuning signal based on the charge pump output signal, and outputs a VCO output signal based on the tuning signal. The demodulator receives an incoming modulated signal and the VCO output signal, and outputs an analog output signal based on the incoming modulated signal and the VCO output signal. The ADC converts the analog output signal into the digital data input signal.

An apparatus includes a processor, a Phase-Locked Loop Waveform Generator (PLLWG), a Voltage Controlled Oscillator (VCO), a demodulator, signal conditioning circuitry, and an Analog-to-Digital Converter (ADC). The processor generates control command signals, receives a digital data input signal, and performs spectrum analysis on the digital data input signal. The PLLWG is coupled to the processor, receives the control command signals, and generates a charge pump output signal based on the control command signals. The VCO is coupled to the PLLWG, receives a tuning signal based on the charge pump output signal, and outputs a VCO output signal based on the tuning signal. The demodulator receives an incoming modulated signal and the VCO output signal, and outputs an analog output signal based on the incoming modulated signal and the VCO output signal. The ADC converts the analog output signal into the digital data input signal.

An encoder system includes a configurable detector array, wherein the configurable detector array includes a plurality of detectors. In an embodiment, the encoder system includes an application-specific integrated circuit (ASIC). The encoder system may also include a memory operable to store a partition map that defines a state for each of the plurality of detectors. In an embodiment, the memory includes a non-volatile memory. The encoder system may also include a controller, such as a microcontroller, operable to read from the memory the partition map and to adjust the partition map according to a misalignment measurement before configuring the configurable detector array. The encoder system may also include an emitter operable to generate a flux modulated by a motion object, wherein the configurable detector array is operable to receive the flux and generate respective current outputs for each of the detectors in response to the flux.

An all-digital voltage monitor (ADVM) generates a multi-bit output code that changes in proportion to a voltage being monitored, by leveraging the voltage impact on a gate delay. ADVM utilizes a simple delay chain, which receives a clock-cycle-long pulse every clock cycle, such that the monitored supply voltage is sampled for one full cycle every cycle. The outputs of all delay cells of the delay chain collectively represents a current voltage state as a digital thermometer code. In AVDM, a voltage droop event thus results in a decrease in the output code from a nominal value, while an overshoot results in an increase in the output code.

The present disclosure may be embodied as an optical encoder system comprising a first optical sensor, a second optical sensor, a first up-down counter, a second up-down counter, and an I/O expander. The optical encoder system may further include a buffer. The present disclosure may also be embodied as an optical encoder system comprising an optical encoder, and a monostable multivibrator. The present disclosure may also be embodied as a method for encoding optical data comprising generating a first optical sensor signal and a second optical sensor signal, converting the first optical sensor signal and second optical sensor signal into four first counter signals, generating a borrow output signal and a carry output signal, converting the borrow output signal and the carry output signal into four second counter signals, and converting the first counter signals and second counter signals into a serial data signal and a serial clock signal.

The present disclosure may be embodied as an optical encoder system comprising a first optical sensor, a second optical sensor, a first up-down counter, a second up-down counter, and an I/O expander. The optical encoder system may further include a buffer. The present disclosure may also be embodied as an optical encoder system comprising an optical encoder, and a monostable multivibrator. The present disclosure may also be embodied as a method for encoding optical data comprising generating a first optical sensor signal and a second optical sensor signal, converting the first optical sensor signal and second optical sensor signal into four first counter signals, generating a borrow output signal and a carry output signal, converting the borrow output signal and the carry output signal into four second counter signals, and converting the first counter signals and second counter signals into a serial data signal and a serial clock signal.

An encoder system includes a configurable detector array, wherein the configurable detector array includes a plurality of detectors. In an embodiment, the encoder system includes an application-specific integrated circuit (ASIC). The encoder system may also include a memory operable to store a partition map that defines a state for each of the plurality of detectors. In an embodiment, the memory includes a non-volatile memory. The encoder system may also include a controller, such as a microcontroller, operable to read from the memory the partition map and to adjust the partition map according to a misalignment measurement before configuring the configurable detector array. The encoder system may also include an emitter operable to generate a flux modulated by a motion object, wherein the configurable detector array is operable to receive the flux and generate respective current outputs for each of the detectors in response to the flux.